MCF5232CVM100J Freescale Semiconductor, MCF5232CVM100J Datasheet - Page 12

• Manufacturer Part Number: MCF5232CVM100J
• Description: IC MCU 64K SRAM 100MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF523xr

Specifications of MCF5232CVM100J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF523x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5234-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Design Recommendations
5.7
5.7.1
5.7.1.1
Table 3
5.7.1.2
See the SDRAM controller module chapter in the MCF5235 Reference Manual for details on address
multiplexing.
5.7.2
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3
standard defines and the FEC module supports 18 signals. These are shown in
12
SD_SRAS
SD_SCAS
DRAMW
SD_CS[1:0]
SD_CKE
BS[3:0]
CLKOUT
shows the behavior of SDRAM signals in synchronous mode.
Interface Recommendations
Signal
SDRAM Controller
Ethernet PHY Transceiver Connection
SDRAM Controller Signals in Synchronous Mode
Address Multiplexing
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SD_CS[1:0], which should not
be interfaced to the SDRAM SD_SRAS signals.
Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled
SD_SCAS on the SDRAM.
DRAM read/write. Asserted for write operations and negated for read operations.
Row address strobe. Select each memory block of SDRAMs connected to the MCF523x. One
SD_CS signal selects one SDRAM block and connects to the corresponding CS signals.
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh mode.
SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing,
setting COC allows SD_CKE to provide command-bit functionality.
Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
Bus clock output. Connects to the CLK input of SDRAMs.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
Transmit clock
Transmit enable
Transmit data
Table 3. Synchronous DRAM Signal Connections
Signal Description
Table 4. MII Mode
Description
ETXCLK
ETXEN
ETXD[3:0]
MCF523x Pin
Table
Freescale Semiconductor
4.