MC9S12C64VFAE Freescale Semiconductor, MC9S12C64VFAE Datasheet - Page 238
![IC MCU 64K FLASH 4K RAM 48-LQFP](/photos/12/39/123982/mc9s12c64vfae_sml.jpg)
MC9S12C64VFAE
Manufacturer Part Number
MC9S12C64VFAE
Description
IC MCU 64K FLASH 4K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C64VFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C64VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
8.3.2.7
This read-only register contains the sequence complete flag, overrun flags for external trigger and FIFO
mode, and the conversion counter.
Read: Anytime
Write: Anytime (no effect on (CC2, CC1, CC0))
238
Module Base + 0x0006
ETORF
Reset
Field
SCF
7
5
W
R
SCF
Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is
cleared when one of the following occurs:
0 Conversion sequence not completed
1 Conversion sequence has completed
External Trigger Overrun Flag — While in edge trigger mode (ETRIGLE = 0), if additional active edges are
detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
following occurs:
0 No External trigger over run error has occurred
1 External trigger over run error has occurred
ATD Status Register 0 (ATDSTAT0)
0
7
A) Write “1” to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and read of a result register
A) Write “1” to ETORF
B) Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
= Unimplemented or Reserved
0
0
6
Figure 8-9. ATD Status Register 0 (ATDSTAT0)
Table 8-13. ATDSTAT0 Field Descriptions
ETORF
MC9S12C-Family / MC9S12GC-Family
0
5
FIFOR
Rev 01.24
0
4
Description
0
0
3
CC2
0
2
Freescale Semiconductor
CC1
0
1
CC0
0
0
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