M37516F8HP#UU Renesas Electronics America, M37516F8HP#UU Datasheet - Page 27

• Manufacturer Part Number: M37516F8HP#UU
• Description: MCU 3/5V 32K PB-FREE 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37516F8HP#UU

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7516 Group
Fig. 22 Structure of serial I/O1 control registers
1. When using the serial I/O1, clear the I
2. When setting the transmit enable bit of serial I/O1 to “1”, the
Rev.1.01
Notes on serial I/O1
bit to “0” or the SDA/SCL interrupt pin selection bit to “0”.
serial I/O1 transmit interrupt request bit is automatically set to
“1”. When not requiring the interrupt occurrence synchronized
with the transmission enalbed, take the following sequence.
abled).
or more instructions have been executed.
abled).
b 7
b 7
Set the serial I/O1 transmit interrupt enable bit to “0” (dis-
Set the transmit enable bit to “1”.
Set the serial I/O1 transmit interrupt request bit to “0” after 1
Set the serial I/O1 transmit interrupt enable bit to “1” (en-
Jul 01, 2003
b 0
b 0
S e r i a l I / O 1 s t a t u s r e g i s t e r
(SIOSTS : address 0019
( U A R T C O N : a d d r e s s 0 0 1 B
U A R T c o n t r o l r e g i s t e r
T r a n s m i t b u f f e r e m p t y f l a g ( T B E )
0 : B u f f e r f u l l
1 : B u f f e r e m p t y
R e c e i v e b u f f e r f u l l f l a g ( R B F )
0 : B u f f e r e m p t y
1 : B u f f e r f u l l
T r a n s m i t s h i f t c o m p l e t i o n f l a g ( T S C )
0 : T r a n s m i t s h i f t i n p r o g r e s s
1 : T r a n s m i t s h i f t c o m p l e t e d
O v e r r u n e r r o r f l a g ( O E )
0 : N o e r r o r
1 : O v e r r u n e r r o r
P a r i t y e r r o r f l a g ( P E )
0 : N o e r r o r
1 : P a r i t y e r r o r
F r a m i n g e r r o r f l a g ( F E )
0 : N o e r r o r
1 : F r a m i n g e r r o r
S u m m i n g e r r o r f l a g ( S E )
0 : ( O E ) U ( P E ) U ( F E ) = 0
1 : ( O E ) U ( P E ) U ( F E ) = 1
N o t u s e d ( r e t u r n s “ 1 ” w h e n r e a d )
C h a r a c t e r l e n g t h s e l e c t i o n b i t ( C H A S )
0 : 8 b i t s
1 : 7 b i t s
P a r i t y e n a b l e b i t ( P A R E )
0 : P a r i t y c h e c k i n g d i s a b l e d
1 : P a r i t y c h e c k i n g e n a b l e d
P a r i t y s e l e c t i o n b i t ( P A R S )
0 : E v e n p a r i t y
1 : O d d p a r i t y
S t o p b i t l e n g t h s e l e c t i o n b i t ( S T P S )
0 : 1 s t o p b i t
1 : 2 s t o p b i t s
P 2
0 : C M O S o u t p u t ( i n o u t p u t m o d e )
1 : N - c h a n n e l o p e n d r a i n o u t p u t ( i n o u t p u t m o d e )
N o t u s e d ( r e t u r n “ 1 ” w h e n r e a d )
5
/ T
X
page 25 of 89
D P - c h a n n e l o u t p u t d i s a b l e b i t ( P O F F )
2
C-BUS interface enable
16
)
1 6
)
b 7
b 0
Serial I/O1 control register
(SIOCON : address 001A
BRG count source selection bit (CSS)
0: f(X
1: f(X
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
1: External clock input when clock synchronous serial
S
0: P2
1: P2
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
1: Serial I/O1 enabled
RDY1
(pins P2
(pins P2
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
I/O1 is selected, external clock input divided by 16
when UART is selected.
7
7
IN
IN
pin operates as ordinary I/O pin
pin operates as S
output enable bit (SRDY)
)
)/4
4
4
to P2
to P2
7
7
operate as ordinary I/O pins)
operate as serial I/O1 pins)
16
)
RDY1
output pin