DF2134BFA20V Renesas Electronics America, DF2134BFA20V Datasheet
DF2134BFA20V
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DF2134BFA20V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2144B, 16 H8S/2134B Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series H8S/2144B HD64F2144B H8S/2134B HD64F2134B Rev.1.00 2005.06 ...
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Rev. 1.00 Jun.24, 2005 Page ii of xxxii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8S/2144B and H8S/2134B are microcomputers (MCUs) made up of the H8S/2000 CPU employing Renesas Technology’s original architecture as their cores, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will ...
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H8S/2144B, H8S/2134B manuals: Manual Title H8S/2144B, H8S/2134B Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual User's manuals for development tools: Manual Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Microcomputer Development Environment System H8S, H8/300 Series ...
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Section 1 Overview ................................................................................................. 1 1.1 Features.................................................................................................................................. 1 1.2 Block Diagram....................................................................................................................... 3 1.3 Pin Arrangements and Functions ........................................................................................... 5 1.3.1 Pin Arrangements ..................................................................................................... 5 1.3.2 Pin Functions in Each Operating Mode .................................................................... 7 1.3.3 Pin Functions .......................................................................................................... 14 Section 2 ...
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Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................... 50 2.7.8 Memory Indirect—@@aa:8 ................................................................................... 50 2.7.9 Effective Address Calculation ................................................................................ 52 2.8 Processing States.................................................................................................................. 54 2.9 Usage Notes ......................................................................................................................... 56 2.9.1 Note on TAS Instruction Usage .............................................................................. 56 2.9.2 Note on STM/LDM ...
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Address Break Control Register (ABRKCR) ......................................................... 81 5.3.3 Break Address Registers (BARA to BARC)............................................... 81 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)...................................................... 82 5.3.5 IRQ Enable Register (IER) ..................................................................................... 83 5.3.6 IRQ Status Register (ISR)....................................................................................... 84 ...
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Basic Operation Timing........................................................................................ 119 6.5.4 Wait Control ......................................................................................................... 127 6.6 Burst ROM Interface.......................................................................................................... 129 6.6.1 Basic Operation Timing........................................................................................ 129 6.6.2 Wait Control ......................................................................................................... 130 6.7 Idle Cycle........................................................................................................................... 131 Section 7 I/O Ports ...............................................................................................133 7.1 Overview............................................................................................................................ 133 7.2 Port 1.................................................................................................................................. ...
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Pin Functions ........................................................................................................ 159 7.7.6 Port 6 Input Pull-Up MOS .................................................................................... 161 7.8 Port 7.................................................................................................................................. 162 7.8.1 Port 7 Input Data Register (P7PIN) ...................................................................... 162 7.8.2 Pin Functions ........................................................................................................ 162 7.9 Port 8.................................................................................................................................. 164 7.9.1 Port 8 Data Direction ...
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Input/Output Pins ............................................................................................................... 199 9.3 Register Descriptions ......................................................................................................... 199 9.3.1 Free-Running Counter (FRC) ............................................................................... 200 9.3.2 Output Compare Registers A and B (OCRA, OCRB) .......................................... 200 9.3.3 Input Capture Registers (ICRA to ICRD) ................................................. 200 9.3.4 ...
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Timer Control/Status Register (TCSR)................................................................. 235 10.3.6 Timer Input Select Register (TISR)...................................................................... 240 10.4 Operation ........................................................................................................................... 240 10.4.1 Pulse Output ......................................................................................................... 240 10.5 Operation Timing............................................................................................................... 242 10.5.1 TCNT Count Timing ............................................................................................ 242 10.5.2 Timing of CMFA and CMFB Setting at ...
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System Reset by RESO Signal (Available for H8S/2144B) ................................. 270 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes ................................................................................................. 270 Section 12 Serial Communication Interface (SCI and IrDA) ..............................271 12.1 Features.............................................................................................................................. 271 12.2 Input/Output Pins ............................................................................................................... ...
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Break Detection and Processing ........................................................................... 322 12.9.3 Mark State and Break Detection ........................................................................... 322 12.9.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) ......................................................................... 322 12.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 322 12.9.6 ...
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Section 15 RAM ..................................................................................................353 Section 16 ROM ..................................................................................................355 16.1 Features.............................................................................................................................. 355 16.2 Mode Transitions ............................................................................................................... 357 16.3 Block Configuration........................................................................................................... 360 16.3.1 Block Configuration ............................................................................................. 360 16.4 Input/Output Pins ............................................................................................................... 361 16.5 Register Descriptions ......................................................................................................... 361 16.5.1 Flash Memory Control Register ...
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Section 18 Power-Down Modes.......................................................................... 389 18.1 Register Descriptions......................................................................................................... 389 18.1.1 Standby Control Register (SBYCR) ..................................................................... 390 18.1.2 Low-Power Control Register (LPWRCR) ............................................................ 392 18.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................... 393 18.2 Mode Transitions and LSI ...
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Flash Memory Characteristics .............................................................................. 496 20.2.7 Usage Note ........................................................................................................... 498 Appendix .............................................................................................................499 A. I/O Port States in Each Processing State............................................................................. 499 B. Product Codes..................................................................................................................... 501 C. Package Dimensions........................................................................................................... 502 Index ...................................................................................................................507 Rev. 1.00 Jun.24, 2005 Page xix of xxxii ...
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Rev. 1.00 Jun.24, 2005 Page xx of xxxii ...
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Section 1 Overview Figure 1.1 Block Diagram of H8S/2144B ...................................................................................... 3 Figure 1.2 Block Diagram of H8S/2134B ...................................................................................... 4 Figure 1.3 Pin Arrangements of H8S/2144B .................................................................................. 5 Figure 1.4 Pin Arrangements of H8S/2134B .................................................................................. 6 Section 2 CPU Figure 2.1 ...
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Figure 5.7 Interrupt Exception Handling...................................................................................... 99 Figure 5.8 Address Break Block Diagram.................................................................................. 101 Figure 5.9 Address Break Timing Example ............................................................................... 103 Figure 5.10 Conflict between Interrupt Generation and Disabling............................................. 104 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of ...
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Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting .................... 214 Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................... 215 Figure 9.13 Timing of Overflow Flag (OVF) Setting................................................................. 216 Figure 9.14 OCRA ...
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Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 292 Figure 12.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) ............................................................................................. 293 Figure 12.5 Sample SCI Initialization Flowchart ....................................................................... 294 Figure 12.6 Example of SCI Transmit Operation ...
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Figure 14.2 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)........................................................ 344 Figure 14.3 A/D Conversion Timing .......................................................................................... 345 Figure 14.4 External Trigger Input Timing ................................................................................ 346 Figure 14.5 A/D Conversion Accuracy Definitions.................................................................... 348 Figure 14.6 A/D ...
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Figure 20.3 Output Load Circuit ................................................................................................ 441 Figure 20.4 System Clock Timing.............................................................................................. 442 Figure 20.5 Oscillation Stabilization Timing.............................................................................. 443 Figure 20.6 Oscillation Stabilization Timing (Leaving Software Standby Mode) ..................... 443 Figure 20.7 Reset Input Timing.................................................................................................. 444 Figure 20.8 Interrupt Input ...
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Figure 20.43 8-Bit Timer Output Timing ................................................................................... 490 Figure 20.44 8-Bit Timer Clock Input Timing ........................................................................... 491 Figure 20.45 8-Bit Timer Reset Input Timing ............................................................................ 491 Figure 20.46 PWMX Output Timing.......................................................................................... 491 Figure 20.47 SCK Clock Input Timing....................................................................................... 491 Figure ...
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Rev. 1.00 Jun.24, 2005 Page xxviii of xxxii ...
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Section 1 Overview Table 1.1 Pin Functions of H8S/2144B in Each Operating Mode ............................................ 7 Table 1.2 Pin Functions of H8S/2134B in Each Operating Mode .......................................... 11 Table 1.3 Pin Functions .......................................................................................................... 14 Section 2 CPU Table 2.1 Instruction Classification ...
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Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration of H8S/2144B.......................................................................... 108 Table 6.2 Pin Configuration of H8S/2134B.......................................................................... 108 Table 6.3 Bus Specifications for Basic Bus Interface........................................................... 113 Address Range for IOS Signal Output.................................................................. 115 Table 6.4 Table 6.5 Data ...
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Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode)................................. 283 Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 287 Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 287 Table 12.6 BRR Settings ...
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Table 20.2 DC Characteristics (3) .......................................................................................... 436 Table 20.2 DC Characteristics (4) .......................................................................................... 438 Table 20.3 Permissible Output Currents................................................................................. 440 Table 20.4 Bus Driving Characteristics .................................................................................. 441 Table 20.5 Clock Timing ........................................................................................................ 442 Table 20.6 Control Signal Timing .......................................................................................... 444 ...
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Features High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions Various peripheral functions 14-bit PWM timer (PWMX) 16-bit free-running timer (FRT) ...
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Section 1 Overview On-chip memory ROM Model Flash memory HD64F2144B version HD64F2134B General I/O ports I/O pins: 74 (H8S/2144B) and 58 (H8S/2134B) Input-only pins: 8 Supports various power-down modes Compact package Product H8S/2144B H8S/2134B Rev. 1.00 Jun.24, 2005 Page 2 ...
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Block Diagram RES XTAL EXTAL MD1 MD0 NMI STBY RESO P97/WAIT P96/ /EXCL P95/AS/IOS P94/HWR P93/RD P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0 P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD P52/SCK0 P51/RxD0 P50/TxD0 Figure ...
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Section 1 Overview RES XTAL EXTAL MD1 MD0 NMI STBY P97/WAIT P96/ /EXCL P95/AS/IOS P94/WR P93/RD P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0 P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD P52/SCK0 P51/RxD0 P50/TxD0 Figure 1.2 ...
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Pin Arrangements and Functions 1.3.1 Pin Arrangements A3/P13 A2/P12 77 A1/P11 78 A0/P10 ...
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Section 1 Overview A3/P13 62 A2/P12 63 A1/P11 64 A0/P10 65 D0/P30 66 D1/P31 67 D2/P32 68 D3/P33 69 ...
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Pin Functions in Each Operating Mode Table 1.1 Pin Functions of H8S/2144B in Each Operating Mode Pin No. FP-100B TFP-100B Mode 1 RES 1 2 XTAL 3 EXTAL 4 VCCB 5 MD1 6 MD0 7 NMI STBY 8 9 ...
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Section 1 Overview Pin No. FP-100B TFP-100B Mode 1 27 P61/FTOA/CIN1/KIN1 28 P62/FTIA/CIN2/KIN2/ TMIY 29 P63/FTIB/CIN3/KIN3 30 (B) PA3/CIN11/KIN11 31 (B) PA2/CIN10/KIN10 32 P64/FTIC/CIN4/KIN4 33 P65/FTID/CIN5/KIN5 34 P66/FTOB/CIN6/KIN6/ IRQ6 35 P67/CIN7/KIN7/IRQ7 36 AVref 37 AVCC 38 P70/AN0 39 P71/AN1 40 ...
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Pin No. FP-100B TFP-100B Mode 1 55 P46/PWX0 56 P47/PWX1 57 PB7/D7 58 PB6/D6 59 VCC 60 A15 61 A14 62 A13 63 A12 64 A11 65 A10 PB5/D5 69 PB4/D4 70 VSS 71 VSS ...
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Section 1 Overview Pin No. FP-100B TFP-100B Mode D10 85 D11 86 D12 87 D13 88 D14 89 D15 90 PB1/D1 91 PB0/D0 92 VSS 93 P80 94 P81 95 P82 96 P83 97 P84/IRQ3/TxD1 98 ...
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Table 1.2 Pin Functions of H8S/2134B in Each Operating Mode Pin No. FP-80A TFP-80C Mode 1 RES 1 2 XTAL 3 EXTAL 4 MD1 5 MD0 6 NMI STBY 7 8 VCL 9 P52/SCK0 10 P51/RxD0 11 P50/TxD0 12 VSS ...
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Section 1 Overview Pin No. FP-80A TFP-80C Mode 1 27 P66/FTOB/CIN6/KIN6/ IRQ6 28 P67/CIN7/KIN7/IRQ7 29 AVCC 30 P70/AN0 31 P71/AN1 32 P72/AN2 33 P73/AN3 34 P74/AN4 35 P75/AN5 36 P76/AN6/DA0 37 P77/AN7/DA1 38 AVSS 39 P40/TMCI0/TxD2/IrTxD 40 P41/TMO0/RxD2/IrRxD 41 P42/TMRI0/SCK2 ...
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Pin No. FP-80A TFP-80C Mode VSS ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 Pin Functions [H8S/2144B] FP-100B, Type Symbol TFP-100B Power VCC 59 VCL 9 VCCB 4 VSS 15, 70, 71, 92 Clock XTAL 2 EXTAL 3 17 EXCL 17 Operating MD1, MD0 5, 6 ...
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FP-100B, Type Symbol TFP-100B RES System 1 control RESO 100 STBY 8 Address A23 to A16 10, 11, 20, 21, bus 30, 31, 47, 48 A15 67 Data bus D15 to D8 ...
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Section 1 Overview [H8S/2144B] FP-100B, Type Symbol TFP-100B AS/IOS Bus 18 control Interrupt NMI 7 signals IRQ0 25, IRQ7 97 to 99, 34, 35 16-bit FTCI 26 free- FTOA 27 running FTOB 34 timer (FRT) FTIA 28 ...
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FP-100B, Type Symbol TFP-100B SCI with IrTxD 49 IrDA IrRxD 50 (SCI_2) Keyboard 10, 11, 20, 21, [H8S/2144B] buffer 30, 31, 47, 48, KIN15 to controller KIN0 26 [H8S/2134B] KIN7 to KIN0 A/D AN7 ...
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Section 1 Overview [H8S/2144B] FP-100B, Type Symbol TFP-100B I/O ports P17 to P10 P27 to P20 P37 to P30 P47 to P40 P52 to P50 ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU 16 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 16-bit register-register divide: 20 states (DIVXU.W) Two CPU operating modes Normal mode Advanced mode Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock ...
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Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. Enhanced instructions Addressing ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's ...
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H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 H'0007 H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode (16 bits) ...
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Section 2 CPU 2.2.2 Advanced Mode Address space Linear access to a maximum address space of 16 Mbytes is possible. Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC bit extended control register (EXR), ...
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Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Section 2 CPU Bit Bit Name Initial Value Undefined 5 H Undefined 4 U Undefined 3 N Undefined 2 Z Undefined 1 V Undefined 0 C Undefined Rev. 1.00 Jun.24, 2005 Page 30 of 510 ...
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Initial Register Values The program counter (PC) among CPU internal registers is initialized when reset exception handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the interrupt mask ...
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Section 2 CPU Data Type Register Number 1-bit data RnH 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH RnL Byte data Figure 2.9 General Register Data Formats (1) Rev. 1.00 Jun.24, 2005 Page 32 ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En [Legend] ERn : General register General register General register R RnH : General register RH RnL ...
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...
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Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* 5 LDM* , STM* MOVFPE* ...
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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description Rd General ...
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Table 2.3 Data Transfer Instructions 1 Instruction Size* Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Subtraction on immediate data ...
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Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function DIVXS B/W Rd Performs signed division on data in two general registers: either 16 bits 8 bits quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares ...
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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on a ...
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Table 2.6 Shift Instructions Instruction Size* Function SHAL B/W/L Rd (shift) SHAR Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. SHLL B/W/L Rd (shift) SHLR Performs a logical shift on data ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower ...
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Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C Logically ...
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Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) ...
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Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the memory operand contents or immediate ...
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Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next; EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number ...
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Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective ...
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Section 2 CPU Table 2.11 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory ...
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The value added is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. Register Indirect with Pre-Decrement—@-ERn: The value ...
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Section 2 CPU 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate ...
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Specified Branch address by @aa:8 (a) Normal Mode Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode Specified Reserved by @aa:8 Branch address (b) Advanced Mode Rev. 1.00 Jun.24, 2005 Page 51 of 510 Section 2 CPU REJ09B0241-0100 ...
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Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table ...
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Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Effective Address Calculation PC contents Sign extension Memory contents Memory contents Rev. 1.00 Jun.24, 2005 Page 53 of 510 Section 2 CPU Effective Address (EA) Sign ...
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Section 2 CPU 2.8 Processing States The H8S/2000 CPU has four main processing states: the reset state, exception handling state, program execution state, and program stop state. Figure 2.13 indicates the state transitions. Reset state In this state the CPU ...
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End of exception handling Exception-handling state RES = high *1 Reset state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition can also be made to the ...
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Section 2 CPU 2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. The TAS instruction is not generated in the H8S, H8/300 Series C/C++ Compiler by Renesas Technology ...
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Prior to executing BCLR: P47 P46 Input/output Input Input Pin state Low High level level DDR BCLR instruction executed: BCLR #0, @P4DDR After executing BCLR: P47 P46 Input/output Output Output Pin state Low High level ...
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Section 2 CPU 2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6 R4L ...
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Section 3 MCU Operating Modes 3.1 MCU Operating Mode Selection This LSI has three operating modes (modes 1 to 3). The operating mode is determined by the setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU ...
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Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit Bit Name Initial Value 7 EXPE —* 6 — All ...
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System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, pin location selection, enables or disables register access to the on-chip peripheral modules, and ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 2 NMIEG 0 1 HIE 0 0 RAME 1 Rev. 1.00 Jun.24, 2005 Page 62 of 510 REJ09B0241-0100 R/W Description R/W NMI Edge Select Selects the valid edge of the ...
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Serial Timer Control Register (STCR) STCR enables or disables register access and on-chip flash memory, and selects the input clock of the timer counter. Bit Bit Name Initial Value 7 IICS All 0 4 IICE 0 ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 3 FLSHE 0 2 — ICKS1 0 0 ICKS0 0 Note: * Available only for the H8S/2144B. Rev. 1.00 Jun.24, 2005 Page 64 of 510 REJ09B0241-0100 R/W Description ...
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Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled. Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and ...
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Section 3 MCU Operating Modes Table 3.2 Pin Functions in Each Mode Port Port 1 Port 2 2 Port A* Port 3 2 Port B* Port 9 P97 P96 P95 to P93 P92 to P91 P90 [Legend] P: I/O port ...
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Address Map in Each Operating Mode Figures 3.1 and 3.2 show the address map in each operating mode. Mode 1 Normal mode Extended on-chip ROM disabled mode H'0000 External address space H'E080 1 On-chip RAM* H'EFFF H'F000 External address ...
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Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended on-chip ROM enabled mode H'0000 H'DFFF H'E080 H'EFFF External address H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Note: * These areas can be used ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority Exception handling is caused by a reset, interrupt, direct transition, or trap instruction as shown in table 4.1. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Exception Source Reset Reserved ...
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Reset The reset exception handling is given the highest priority. When the RES signal goes low, all processing halts and this LSI enters the reset state. When the power is turned on, hold the RES signal low for at ...
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Section 4 Exception Handling RES Internal address bus Internal read signal Internal write signal Internal data bus (1) Reset exception handling vector address ((1) = H'0000) (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) ...
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Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ7 to IRQ0, and KIN15 to KIN0) and internal interrupt sources from the on-chip peripheral modules. NMI ...
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Section 4 Exception Handling Table 4.3 Status of CCR after Trap Instruction Exception Handling Interrupt Control Mode 0 1 [Legend] 1: Set to 1 —: Retains value prior to execution 4.6 Stack Status after Exception Handling Figure 4.2 shows the ...
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Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should ...
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Section 4 Exception Handling Rev. 1.00 Jun.24, 2005 Page 76 of 510 REJ09B0241-0100 ...
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Section 5 Interrupt Controller 5.1 Features Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). Priorities settable with ICR An interrupt control ...
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Section 5 Interrupt Controller SYSCR NMI input IRQ input KIN input Internal interrupt request WOVI0 to TEI2 Interrupt controller [Legend] Interrupt control register ICR: IRQ sense control register ISCR: IRQ enable register IER: IRQ status register ISR: Keyboard matrix interrupt ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol I/O NMI Input IRQ7 to IRQ0 Input KIN15 to KIN0 Input (KIN7 to KIN0)* Note: H8S/2134B * 5.3 Register Descriptions The interrupt controller ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers (ICRA to ICRC) The ICR registers set interrupt control levels for interrupts other than NMI and address breaks. The correspondence between interrupt sources and ICRA to ICRC settings is ...
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Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set address break is requested. Bit Bit Name Initial Value 7 CMF 0 6 — All 0 ...
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Section 5 Interrupt Controller BARB Bit Bit Name Initial Value 7 A15 All BARC Bit Bit Name Initial Value 7 A7 All — 0 5.3.4 IRQ Sense Control Registers ...
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ISCRL Bit Bit Name Initial Value 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 5.3.5 IRQ Enable Register (IER) IER controls the enabling and ...
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Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests. Bit Bit Name Initial Value 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 ...
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Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) KMIMRA and KMIMR mask each key-sensing input (KIN15 to KIN0) interrupt. To make the settings of these registers valid, clear bit MSTP2 in MSTPCRL to 0. KMIMRA Bit Bit Name Initial Value ...
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Section 5 Interrupt Controller KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 KMIMR8 (initial value 1) PA0/KIN8 KMIMR9 (initial value 1) PA1/KIN9 KMIMR15 (initial value 1) PA7/KIN15 Figure ...
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Interrupt Sources 5.4.1 External Interrupts There are three types of external interrupts: NMI, IRQ7 to IRQ0 and KIN15 to KIN0. KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the IRQ6 interrupt source. Of these, ...
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Section 5 Interrupt Controller IRQnSCA, IRQnSCB detection circuit IRQn input Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to ...
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Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following features: 1. For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of ...
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Section 5 Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source Name External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8 — Reserved for system use ...
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Origin of Interrupt Source Name TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use TMR_Y CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) Reserved for system use — Reserved for system use ...
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Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break ...
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Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling ...
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Section 5 Interrupt Controller An interrupt with interrupt control level 1? IRQ0 Yes Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 1.00 Jun.24, 2005 Page 94 of 510 REJ09B0241-0100 Program excution state Interrupt ...
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Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR ...
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Section 5 Interrupt Controller interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending interrupt request with interrupt control level ...
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Program excution state Interrupt generated? Yes An interrupt with interrupt control level 1? Yes No IRQ0 No Yes IRQ1 Yes TEI2 Yes Yes Yes Save PC and CCR Read vector address Branch to interrupt handling routine Figure ...
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Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...
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Figure 5.7 Interrupt Exception Handling Section 5 Interrupt Controller Rev. 1.00 Jun.24, 2005 Page 99 of 510 REJ09B0241-0100 ...
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Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.5 shows interrupt response times the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table ...
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Address Break 5.7.1 Features This LSI can determine the specific address prefetch by the CPU to generate an address break interrupt by setting ABRKCR and BAR address break interrupt is generated, the address break interrupt exception handling ...
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Section 5 Interrupt Controller 2. Set the BIE bit in ABRKCR enable the address break. When the BIE bit is cleared address break is not requested. When the setting conditions are satisfied, the CMF ...
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When a break address specified instruction is executed for one state in the program area and on-chip memory Instruction Instruction Instruction fetch fetch fetch φ H'0310 H'0312 H'0314 H'0316 Address bus NOP NOP execution execution Break request signal H'0310 ...
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Section 5 Interrupt Controller 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable ...
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Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit ...
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Section 5 Interrupt Controller Rev. 1.00 Jun.24, 2005 Page 106 of 510 REJ09B0241-0100 ...
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Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that can specify the bus settings such as the bus width and the number of access cycles of the external address space. 6.1 Features Basic bus interface ...
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Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Tables 6.1 and 6.2 summarize the pin configuration of the bus controller. Table 6.1 Pin Configuration of H8S/2144B Symbol I/O AS Output IOS Output RD Output HWR Output LWR Output WAIT Input ...
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Register Descriptions The bus controller has the following registers. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR). Bus control register (BCR) Wait state control register (WSCR) 6.3.1 Bus Control Register (BCR) BCR ...
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value 3 BRSTS0 IOS1 1 0 IOS0 1 6.3.2 Wait State Control Register (WSCR) WSCR is used to specify the data bus width for external address space ...
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Bit Bit Name Initial Value 4 AST 1 3 WMS1 0 2 WMS0 0 1 WC1 1 0 WC0 1 Note: * Setting prohibited in the H8S/2134B. R/W Description R/W Access State Control Selects access cycles for ...
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Section 6 Bus Controller (BSC) 6.4 Bus Control 6.4.1 Bus Specifications The external address space bus specifications consist of three elements: Bus width, the number of access cycles, and the wait mode and the number of program wait cycles. The ...
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Table 6.3 shows the bus specifications for the basic bus interface of each area. Table 6.3 Bus Specifications for Basic Bus Interface ABW AST WMS1 WMS0 WC1 0 0 — — —* — — — ...
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Section 6 Bus Controller (BSC) 6.4.3 Normal Mode The external address space is initialized as the basic bus interface and a 3-state access space. In on-chip ROM disable extended mode, the address space other than on-chip RAM and internal I/O ...
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Address Range for IOS Signal Output Table 6.4 IOS1 IOS0 IOS Signal Output Range H'(FF)F000 to H'(FF)F03F H'(FF)F000 to H'(FF)F0FF H'(FF)F000 to H'(FF)F3FF H'(FF)F000 to H'(FF)F7FF Section 6 Bus Controller (BSC) (Initial value) Rev. ...
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Section 6 Bus Controller (BSC) 6.5 Basic Bus Interface The basic bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications when using the basic bus interface, see table 6.3 6.5.1 Data Size ...
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Byte size Byte size Word size Longword size Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes Table 6.5 shows the data buses used and valid strobes for each access space read, the ...
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Section 6 Bus Controller (BSC) Table 6.5 Data Buses Used and Valid Strobes Access Read/ Area Size Write 8-bit access Byte Read space Write 16-bit access Byte Read space [H8S/2144B] Write Word Read Write Note: Undefined: Undefined data is output. ...
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Basic Operation Timing 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper byte (D15 to D8) of the data bus is used in ...
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Section 6 Bus Controller (BSC) 8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper byte (D15 to D8) of the data bus is used ...
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Access Space [Available for H8S/2144B]: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper byte (D15 to D8) of the data bus is used for ...
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Section 6 Bus Controller (BSC) Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) D15 to D8 Read Write D15 Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte ...
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Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD D15 to D8 Read HWR LWR Write D15 Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Section 6 ...
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Section 6 Bus Controller (BSC) 16-Bit, 3-State Access Space [Available for H8S/2144B]: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper byte (D15 to D8) of the ...
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Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD D15 to D8 Read HWR LWR Write D15 Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) Section ...
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Section 6 Bus Controller (BSC) Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD D15 to D8 Read HWR LWR Write D15 Figure 6.12 Bus Timing for 16-Bit, 3-State Access ...
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Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait cycles (T ). There are three ways of inserting wait cycles: Program wait insertion, pin W wait insertion ...
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Section 6 Bus Controller (BSC) WAIT Address bus AS/IOS (IOSE = 0) RD Read Data bus HWR, LWR Write Data bus Note: ↓ shown in clock indicates the WAIT pin sampling timing. Figure 6.13 Example of Wait Cycle Insertion Timing ...
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Burst ROM Interface In this LSI, the external address space can be designated as the burst ROM space by setting the BRSTRM bit in BCR to 1, and the burst ROM interface enabled. Consecutive burst accesses of a maximum ...
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Section 6 Bus Controller (BSC) Address bus AS/IOS (IOSE = 0) RD Data bus Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control As with the basic bus interface, program wait insertion ...
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Idle Cycle When this LSI accesses the external address space, it can insert a 1-state idle cycle (T bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for ...
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Section 6 Bus Controller (BSC) Table 6.6 Pin States in Idle Cycle Pins (H8S/2144B) Pins (H8S/2134B) Pin State A23 to A0, IOS A15 to A0, IOS D15 HWR, LWR WR Rev. ...
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Overview In the H8S/2144B, ten I/O ports (ports and B) and one input-only port (port 7) are included. In the H8S/2134B, eight I/O ports (ports and 9) and one ...
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Section 7 I/O Ports Table 7.1 Port Functions of H8S/2144B Port Description Port 1 General I/O port also functioning as address output pin Port 2 General I/O port also functioning as address output pin Port 3 General I/O port also ...
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Port Description Port 4 General I/O port also functioning as PWMX output, TMR_0 and TMR_1 input/output, SCI_2 input/output, and IrDA interface input/output pins Port 5 General I/O port also functioning as SCI_0 input/output pins Port 6 General I/O port also ...
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Section 7 I/O Ports Port Description Port 8 General I/O port also functioning as interrupt input and SCI_1 input/output pins Port 9 General I/O port also functioning as extended data bus control input/output, subclock input, output, interrupt input, and A/D ...
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Port Description Port B General I/O port also functioning as data bus input/output pins Table 7.2 Port Functions of H8S/2134B Port Description Port 1 General I/O port also functioning as address output pin Port 2 General I/O port also functioning ...
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Section 7 I/O Ports Port Description Port 3 General I/O port also functioning as data bus input/output pin Port 4 General I/O port also functioning as PWMX output, TMR_0 and TMR_1 input/output, SCI_2 input/output, and IrDA interface input/output pins Port ...
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Port Description Port 7 General input port also functioning as A/D converter analog input and D/A converter analog output pins Port 8 General I/O port also functioning as interrupt input and SCI_1 input/output pins Port 9 General I/O port also ...
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Section 7 I/O Ports 7.2 Port 1 Port 8-bit I/O port. Port 1 pins also function as address output pins. Port 1 functions change according to the operating mode. Port 1 has an on-chip input pull-up MOS ...
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Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value 7 P17DR 0 6 P16DR 0 5 P15DR 0 4 P14DR 0 3 P13DR 0 2 P12DR 0 1 P11DR ...
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Section 7 I/O Ports 7.2.4 Pin Functions P17/A7, P16/A6, P15/A5, P14/A4, P13/A3, P12/A2, P11/A1, and P10/A0 Pin functions are switched as shown below according to the combination of the P1nDDR bit and operating mode. Operating Mode Mode 1 P1nDDR — ...
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Port 2 Port 8-bit I/O port. Port 2 pins also function as address bus output pins. Port 2 functions change according to the operating mode. Port 2 has an on-chip input pull-up MOS function that can ...
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Section 7 I/O Ports 7.3.2 Port 2 Data Register (P2DR) P2DR stores output data for port 2. Bit Bit Name Initial Value 7 P27DR 0 6 P26DR 0 5 P25DR 0 4 P24DR 0 3 P23DR 0 2 P22DR 0 ...
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Pin Functions To ensure normal access to external space, P27 should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. P27/A15, P26/A14, P25/A13, and P24/A12 Pin functions are ...
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Section 7 I/O Ports Table 7.4 Input Pull-Up MOS States (Port 2) Mode Reset 1 Off 2, 3 [Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P2DDR = 0, and ...
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Port 3 Port 8-bit I/O port. Port 3 pins also function as a bidirectional data bus. Port 3 functions change according to the operating mode. Port 3 has the following registers. Port 3 data direction register ...
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Section 7 I/O Ports 7.4.3 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the port 3 on-chip input pull-up MOSs on a bit-by-bit basis. Bit Bit Name Initial Value 7 P37PCR 0 6 P36PCR 0 5 P35PCR 0 4 ...
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Table 7.5 Input Pull-Up MOS States (Port 3) Mode Reset (EXPE = 1) Off 2, 3 (EXPE = 0) [Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, ...
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Section 7 I/O Ports 7.5 Port 4 Port 8-bit I/O port. Port 4 pins also function as PWMX output pins, TMR_0 and TMR_1 I/O pins, SCI_2 I/O pins, and IrDA interface I/O pins. Port 4 pin functions ...
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Pin Functions P47/PWX1 Pin functions are switched as shown below according to the combination of the OEB bit in DACR of the 14-bit PWM and the P47DDR bit. OEB P47DDR 0 Pin Function P47 input pin P46/PWX0 Pin functions ...
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Section 7 I/O Ports P43/TMCI1 Pin functions are switched as shown below according to the P43DDR bit. P43DDR Pin Function Note: When the external clock is selected by bits CKS2 to CKS0 in TCR1 of TMR_1, this pin * is ...
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P40/TMCI0/TxD2/IrTxD Pin functions are switched as shown below according to the combination of the TE bit in SCR of SCI_2 and the P40DDR bit. TE P40DDR Pin Function Note: * When an external clock is selected with bits CKS2 to ...
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Section 7 I/O Ports 7.6 Port 5 Port 3-bit I/O port. Port 5 pins also function as SCI_0 I/O pins. Port 5 has the following registers. Port 5 data direction register (P5DDR) Port 5 data register (P5DR) ...
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Pin Functions P52/SCK0 Pin functions are switched as shown below according to the combination of the CKE1 and CKE0 bits in SCR of SCI_0, the C/A bit in SMR of SCI_0, the ICE bit in ICCR of IIC_0, and ...
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Section 7 I/O Ports 7.7 Port 6 Port 8-bit I/O port. Port 6 pins also function as the FRT I/O pins, the TMR_Y input pin, key-sense interrupt input pins, extended A/D converter input pins, and external interrupt ...
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Port 6 Data Register (P6DR) P6DR stores output data for port 6. Bit Bit Name Initial Value 7 P67DR 0 6 P66DR 0 5 P65DR 0 4 P64DR 0 3 P63DR 0 2 P62DR 0 1 P61DR 0 0 ...
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Section 7 I/O Ports 7.7.4 System Control Register 2 (SYSCR2) SYSCR2 controls the signal levels input on port 6 and current specifications. Bit Bit Name Initial Value 7 KWUL1 0 6 KWUL0 0 5 P6PUE 0 4 — ...
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Pin Functions P67/CIN7/KIN7/IRQ7 Pin functions are switched as shown below according to the P67DDR bit. P67DDR Pin Function This pin is used as the IRQ7 input pin when bit IRQ7E is set IER. It can always ...
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Section 7 I/O Ports P63/FTIB/CIN3/KIN3 P63DDR Pin Function This pin can always be used as the FTIB, KIN3, or CIN3 input pin. Note: * P62/FTIA/CIN2/KIN2/TMIY P62DDR Pin Function This pin can always be used as the FTIA, TMIY, KIN2, or ...
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Port 6 Input Pull-Up MOS Port 6 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified off on a bit-by-bit basis. The input pull-up ...
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Section 7 I/O Ports 7.8 Port 7 Port 8-bit input only port. Port 7 pins also function as the A/D converter analog input pins and D/A converter analog output pins. Port 7 functions are the same in ...
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P76/AN6/DA0 Pin functions are switched as shown below according to the combination of the DAE bit in DACR of the D/A converter and the DAOE0 bit. DAOE0 DAE Pin Function P76 input pin Note: This pin can always be used ...
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Section 7 I/O Ports 7.9 Port 8 Port 8-bit I/O port. Port 8 pins also function as SCI_1 I/O pins and interrupt input pins. Port 8 pin functions are the same in all operating modes. Port 8 ...
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Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins (P86 to P80). Bit Bit Name Initial Value 7 — P86DR 0 5 P85DR 0 4 P84DR 0 3 P83DR 0 2 P82DR ...
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Section 7 I/O Ports P85/IRQ4/RxD1 Pin functions are switched as shown below according to the combination of the RE bit in SCR of SCI_1 and the P85DDR bit. RE P85DDR Pin Function When the IRQ4E bit in IER is set ...