MC68331MEH16 Freescale Semiconductor, MC68331MEH16 Datasheet - Page 20

• Manufacturer Part Number: MC68331MEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331MEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

3.2.5 Spurious Interrupt Monitor
3.2.6 Software Watchdog
SWSR —Software Service Register
3.2.7 Periodic Interrupt Timer
PICR — Periodic Interrupt Control Register
PIRQL[2:0] —Periodic Interrupt Request Level
20
RESET:
RESET:
15
15
0
0
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-ac-
knowledge cycle.
The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that
a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watch-
dog times out and issues a reset. This register can be written at any time, but returns zeros when read.
Register shown with read value
Perform a software watchdog service sequence as follows:
Both writes must occur before time-out in the order listed, but any number of instructions can be exe-
cuted between the two writes.
The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown
in the following table.
The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing
for the PIT is provided by a programmable prescaler driven by the system clock.
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be
read or written at any time. Bits [15:11] are unimplemented and always return zero.
The following table shows what interrupt request level is asserted when a periodic interrupt is generat-
ed. If a PIT interrupt and an external IRQ signal of the same priority occur simultaneously, the PIT in-
terrupt is serviced first. The periodic timer continues to run when the interrupt is disabled.
1. Write $55 to SWSR.
2. Write $AA to SWSR.
14
0
0
13
0
0
NOT USED
12
0
0
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
0
10
0
Go to: www.freescale.com
MODCLK
PIRQL
0
0
1
8
8
0
7
0
0
7
0
SWP
1
0
6
0
0
0
5
0
0
0
4
0
0
0
PIV
3
0
0
1
2
0
0
1
MC68331TS/D
$YFFA27
1
0
0
$YFFA22
1
0
0
0
0
1