MC68HC11K1CFUE3 Freescale Semiconductor, MC68HC11K1CFUE3 Datasheet - Page 31

• Manufacturer Part Number: MC68HC11K1CFUE3
• Description: MCU 8-BIT 768 RAM 3MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11K1CFUE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

4.3.1 Program Chip Select (CSPROG)
4.3.2 I/O Chip Select (CSIO)
M68HC11 K Series
MC68HC11KTS/D
The program chip select (CSPROG) is active in the range of memory where the main program exists.
CSPROG is enabled out of reset in all modes. After reset in normal mode, the PCS stretch select bit is
set to provide one cycle of stretch so that slow memory devices can be used.
The I/O chip select (CSIO) is programmable for a four Kbyte size located at addresses $1000 to $1FFF
or eight Kbyte size located at addresses $0000 to $1FFF. Polarity of the active state is programmable
for active high or active low. Clock stretching can be set from zero to three cycles.
CSPROG
CSGP1,
CSGP2
CSIO
Enable
Valid
Polarity
Size
Start Address
Stretch
Enable
Valid
Polarity
Size
Start Address
Stretch
Priority
Enable
Valid
Polarity
Size
Start Address
Stretch
Other
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IOEN in CSCTL —1 = On, off at reset (0)
IOCSA in CSCTL —1 = Address valid, 0 = E valid
IOPL in CSCTL —1 = Active high, 0 = Active low
IOSZ in CSCTL —1 = 4K ($1000–$1FFF), 0 = 8K ($0000–$1FFF)
Fixed (see Size)
IO1SA:IO1SB in CSCSTR —0, 1, 2, or 3 E clocks
PSCEN in CSCTL —1 = On, ON at reset
Fixed (Address valid)
Fixed (Active low)
PCSZA:PCSZB in CSCTL —
Fixed (see Size)
PCSA:PCSB in CSCSTR —0, 1, 2, or 3 E clocks
GCSPR in CSCTL —
Set size to 0K to disable
GxPOL in GPCS1C (GPCS2C) —1 = Address valid, 0 = E valid
GxAV in GPCS1C (GPCS2C) —1 = Active high, 0 = Active low
Refer to GPCS1C (GPCS2C) —2K to 512K in nine steps, 0K = dis-
able, can also follow memory expansion window 1 or window 2
Refer to GPCS1A (GPCS2A)
Refer to CSCSTR —0, 1, 2, or 3 E clocks
G1DG2 in GPCS1C allows CSGP1 and CSGP2 to be connected to
an internal OR gate and driven out the CSGP2 pin.
G1DPC in GPCS1C allows CSGP1 and CSPROG to be connected to
an internal OR gate and driven out the CSPROG pin.
G2DPC in GPCS2C allows CSGP2 and CSPROG to be connected to
an internal OR gate and driven out the CSPROG pin.
MXGS2 in MMSIZ allows CSGP2 to follow either 64K CPU addresses
or 512K expansion addresses.
MXGS1 in MMSIZ allows CSGP1 to follow either 64K CPU addresses
or 512K expansion addresses.
1 = CSGPx above CSPROG
0 = CSPROG above CSGPx
0:0 = 64K ($0000–$FFFF)
0:1 = 32K ($8000–$FFFF)
1:0 = 16K ($C000–$FFFF)
1:1 = 8K ($E000–$FFFF)
MOTOROLA
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