MCF5235CVM100J Freescale Semiconductor, MCF5235CVM100J Datasheet - Page 10
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MCF5235CVM100J
Manufacturer Part Number
MCF5235CVM100J
Description
IC MCU 64K 100MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF523xr
Datasheet
1.MCF5232CVM100J.pdf
(48 pages)
Specifications of MCF5235CVM100J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
113
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF523x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5234-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5235CVM100J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Design Recommendations
5.2
5.2.1
Figure 1
OV
5.2.1.1
If OV
connected to the OV
up before V
power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the
power supplies should be slower than 1 μs to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
10
DD
•
1. Use 1 ms or slower rise time for all supplies.
2. V
DD
is specified relative to V
33 μF, 0.1 μF, and 0.01 μF across each power supply
OV
voltage regulator.
shows situations in sequencing the I/O V
is powered up with V
DD
Power Supply
DD
DD
Supply Voltage Sequencing and Separation Cautions
and OV
Power Up Sequence
going to the higher external voltages. One way to accomplish this is to use a low drop-out
must power up. V
3.3V
2.5V
1.5V
DD
DD
Notes:
0
Figure 1. Supply Voltage Sequencing and Separation Cautions
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
1.
2.
3.
4.
/V
to be in a high impedance state. There is no limit on how long after OV
VDD should not exceed OVDD or VDDPLL by more than 0.4 V
at any time, including power-up.
Recommended that VDD should track OVDD/VDDPLL up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD,
VDD, or VDDPLL) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.
DDPLL
DD
1
DD
should track up to 0.9 V, then separate for the completion of ramps with
DD
at 0 V, then the sense circuits in the I/O pads cause all pad output drivers
.
2
should not lead the OV
Supplies Stable
DD
(OV
DD
), PLL V
DD
or V
DDPLL
DD
(V
OV
V
DD
DDPLL
by more than 0.4 V during
DD,
V
DDPLL
), and Core V
Time
Freescale Semiconductor
DD
DD
powers
(V
DD
).