MC68HC711E9MFNE2 Freescale Semiconductor, MC68HC711E9MFNE2 Datasheet - Page 206

IC MCU 8BIT 512BYTES ROM 52-PLCC

MC68HC711E9MFNE2

Manufacturer Part Number
MC68HC711E9MFNE2
Description
IC MCU 8BIT 512BYTES ROM 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E9MFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Timing System
9.8.2 Pulse Accumulator Count Register
Technical Data
206
Address:
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
This 8-bit read/write register contains the count of external input events
at the PAI input or the accumulated count. The PACNT is readable even
if PAI is not active in gated time accumulation mode. The counter is not
affected by reset and can be read or written at any time. Counting is
synchronized to the internal PH2 clock so that incrementing and reading
occur during opposite half cycles.
Reset:
Read:
Write:
Refer to
Refer to
Figure 9-26. Pulse Accumulator Count Register (PACNT)
0 = Output compare 5 function enable (no IC4)
1 = Input capture 4 function enable (no OC5)
$1027
Bit 7
Bit 7
Section 6. Parallel Input/Output (I/O)
9.6 Real-Time Interrupt
Bit 6
Timing System
6
Bit 5
5
Indeterminate after reset
Bit 4
4
(RTI).
Bit 3
3
M68HC11E Family — Rev. 3.2
Bit 2
2
Ports.
Bit 1
1
MOTOROLA
Bit 0
Bit 0

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