DF2145BVTE10 Renesas Electronics America, DF2145BVTE10 Datasheet
DF2145BVTE10
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DF2145BVTE10 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2140B Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that ...
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The H8S/2140B Group are microcomputers (MCUs) made up of the H8S/2000 CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general ...
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In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. In order to understand the details of a register when its name is known Read the index that is the final part ...
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Main Revisions for This Edition Item Page All — 1.1 Features 1 2 1.2 Block Diagram 3 Figure 1.1 Internal Block Diagram of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B Figure 1.2 Internal 4 Block Diagram of H8S/2160B and H8S/2161B Revision (See ...
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Item Page 1.3.1 Pin 5 Arrangement Figure 1.3 Pin Arrangement of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B 1.3.2 Pin Functions in 11 Each Operating Mode Table 1.1 Pin Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B in Each Operating Mode 2.4.4 Condition-Code ...
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Item Page 2.7.9 Effective 56 Address Calculation Table 2.13 Effective Address Calculation (2) 3.4 Address Map in 77, 78 Each Operating Mode Figure 3.7 Address Map for H8S/2145B (1) Figure 3.8 Address Map for H8S/2145B (2) Figure 3.9 Address 79 ...
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Item Page 5.6 Interrupt Control 105 Modes and Interrupt Operation Table 5.4 Interrupt Control Modes 5.6.5 DTC Activation 114 by Interrupt 7.2.8 DTC Vector 151 Register (DTVECR) 7.4 Location of 154 Register Information and DTC Vector Table Table 7.1 Interrupt ...
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Item Page 8.9.3 Pin Functions 197 198 199 8.12.4 Pin Functions 213 to 215 11.3.6 Timer Interrupt 265 Enable Register (TIER) 12.7 Input Capture 307 Operation Figure 12.11 Timing of Input Capture Operation Figure 12.12 Timing 307 of Input Capture ...
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Item Page 14.4.2 Interval Timer 354 Mode Figure 14.4 OVF Flag Set Timing 14.6.2 Conflict 357 between Timer Counter (TCNT) Write and Increment Figure 14.7 Conflict between TCNT Write and Increment 15.1 Features 360 Figure 15.1 Block Diagram of SCI ...
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Item Page 2 16.3 Bus 427, 428 Table amended Register (ICCR) Table 16.5 Flash and 430 Transfer States (Slave Mode) 16.4.4 Master 451 Receive Operation Figure 16.12 Example of Operation Timing in Master Receive Mode (MLS = WAIT ...
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Item Page 16.4.4 Master 453 Receive Operation Figure 16.15 Sample Flowchart for Operations in Master Receive (Receiving a Single Byte) (WAIT = 1) Figure 16.16 Example 456 of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = ...
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Item Page 17.3.1 Keyboard 492 Control Register H (KBCRH) 19.4.4 Host Interface 569 Shutdown Function (LPCPD) Table 19.5 Scope of Host Interface Pin Shutdown Section 22 RAM 601 Section 23 ROM 603 Revision (See Manual for Details) Table amended Bit ...
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Item Page 23.8.1 Program/ 625 Program-Verify Figure 23.11 Program/Program- Verify Flowchart Section 24 Clock 633 Pulse Generator Figure 24.1 Block Diagram of Clock Pulse Generator 24.5 Subclock Input 639 Circuit 25.1.1 Standby 643 Control Register (SBYCR) Rev. 3.00 Mar 21, ...
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Item Page 25.1.1 Standby 643 Control Register (SBYCR) Table 25.1 Operating Frequency and Wait Time 26.1 Register 670 Addresses (Address Order) 26.2 Register Bits 679 26.3 Register States 688 in Each Operating Mode 26.4 Register Select 690 Conditions 27.1.1 Absolute ...
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Item Page 27.1.6 Flash Memory 722 Characteristics Table 27.15 Flash Memory Characteristics 723 27.2.2 DC 736 Characteristics Table 27.17 DC Characteristics (5) 27.2.3 AC 752 Characteristics Table 27.23 Timing of On-Chip Peripheral Modules (1) 27.2.7 Usage Notes 761 Figure 27.5 ...
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Item Page 27.3.1 Clock Timing 762 Figure 27.7 Oscillation Settling Timing Appendix B Product 779 Codes Appendix C Package 780 Dimensions Figure C.1 Package Dimensions (FP-100B) Figure C.2 Package 781 Dimensions (TFP-100B) Figure C.3 Package 782 Dimensions (TFP-144) Revision (See ...
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Rev. 3.00 Mar 21, 2006 page xx of liv ...
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Section 1 Overview ............................................................................................................. 1.1 Features ............................................................................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Arrangement and Functions........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... 18 Section 2 CPU ...................................................................................................................... 25 2.1 Features ...
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Memory Indirect—@@aa:8 ................................................................................ 54 2.7.9 Effective Address Calculation ............................................................................. 55 2.8 Processing States............................................................................................................... 57 2.9 Usage Notes ...................................................................................................................... 59 2.9.1 Note on TAS Instruction Usage ........................................................................... 59 2.9.2 Note on STM/LDM Instruction Usage ................................................................ 59 2.9.3 Note on Bit ...
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IRQ Sense Control Registers (ISCRH, ISCRL)................................................... 95 5.3.5 IRQ Enable Register (IER) .................................................................................. 96 5.3.6 IRQ Status Register (ISR).................................................................................... 96 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Interrupt Mask Register (WUEMRB) ....................................... 97 5.4 Interrupt ...
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Basic Operation Timing ....................................................................................... 131 6.5.4 Wait Control ........................................................................................................ 139 6.6 Burst ROM Interface......................................................................................................... 141 6.6.1 Basic Operation Timing ....................................................................................... 141 6.6.2 Wait Control ........................................................................................................ 142 6.7 Idle Cycle .......................................................................................................................... 142 6.8 Bus Arbitration.................................................................................................................. 144 6.8.1 Priority of Bus ...
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Setting Required on Entering Subactive Mode or Watch Mode .......................... 166 7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter ........ 166 Section 8 I/O Ports .............................................................................................................. 167 8.1 Overview........................................................................................................................... 167 8.2 Port 1................................................................................................................................. 172 ...
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Port 8................................................................................................................................. 195 8.9.1 Port 8 Data Direction Register (P8DDR)............................................................. 195 8.9.2 Port 8 Data Register (P8DR)................................................................................ 196 8.9.3 Pin Functions ....................................................................................................... 196 8.10 Port 9................................................................................................................................. 199 8.10.1 Port 9 Data Direction Register (P9DDR)............................................................. 200 8.10.2 Port 9 Data ...
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Section 9 8-Bit PWM Timer (PWM) 9.1 Features ............................................................................................................................. 231 9.2 Input/Output Pin................................................................................................................ 233 9.3 Register Descriptions ........................................................................................................ 233 9.3.1 PWM Register Select (PWSL)............................................................................. 234 9.3.2 PWM Data Registers (PWDR0 to PWDR15) ...................................................... 236 9.3.3 PWM Data Polarity Registers A ...
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FRC Increment Timing ........................................................................................ 272 11.5.2 Output Compare Output Timing .......................................................................... 273 11.5.3 FRC Clear Timing................................................................................................ 273 11.5.4 Input Capture Input Timing ................................................................................. 274 11.5.5 Buffered Input Capture Input Timing .................................................................. 274 11.5.6 Timing of Input Capture Flag (ICF) ...
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Count Mode .............................................................................................. 305 12.6.2 Compare-Match Count Mode .............................................................................. 306 12.7 Input Capture Operation.................................................................................................... 306 12.8 Interrupt Sources............................................................................................................... 309 12.9 Usage Notes ...................................................................................................................... 310 12.9.1 Conflict between TCNT Write and Clear ............................................................ 310 12.9.2 Conflict between TCNT Write ...
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Operation .......................................................................................................................... 352 14.4.1 Watchdog Timer Mode ........................................................................................ 352 14.4.2 Interval Timer Mode ............................................................................................ 354 14.4.3 RESO Signal Output Timing ............................................................................... 355 14.5 Interrupt Sources............................................................................................................... 355 14.6 Usage Notes ...................................................................................................................... 356 14.6.1 Notes on Register Access..................................................................................... 356 14.6.2 Conflict ...
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SCI Initialization (Clocked Synchronous Mode) ................................................. 394 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 395 15.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 398 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 400 15.7 IrDA Operation ...
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Initialization of Internal State .............................................................................. 473 16.5 Interrupt Sources............................................................................................................... 475 16.6 Usage Notes ...................................................................................................................... 475 16.6.1 Module Stop Mode Setting .................................................................................. 488 Section 17 Keyboard Buffer Controller 17.1 Features ............................................................................................................................. 489 17.2 Input/Output Pins .............................................................................................................. 491 17.3 Register Descriptions ...
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IBF1, IBF2, IBF3, and IBF4 ................................................................................ 525 18.5.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................ 525 18.6 Usage Notes ...................................................................................................................... 527 18.6.1 Note on Host Interface ......................................................................................... 527 18.6.2 Module Stop Mode Setting .................................................................................. 527 Section 19 Host Interface ...
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Module Stop Mode Setting .................................................................................. 583 Section 21 A/D Converter 21.1 Features ............................................................................................................................. 585 21.2 Input/Output Pins .............................................................................................................. 587 21.3 Register Descriptions ........................................................................................................ 588 21.3.1 A/D Data Registers (ADDRA to ADDRD).............................................. 588 21.3.2 A/D Control/Status Register ...
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Boot Mode ........................................................................................................... 618 23.7.2 User Program Mode............................................................................................. 622 23.8 Flash Memory Programming/Erasing ............................................................................... 623 23.8.1 Program/Program-Verify ..................................................................................... 624 23.8.2 Erase/Erase-Verify............................................................................................... 626 23.9 Program/Erase Protection ................................................................................................. 628 23.9.1 Hardware Protection ............................................................................................ 628 23.9.2 Software Protection.............................................................................................. 628 23.9.3 Error Protection.................................................................................................... ...
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Module Stop Mode ........................................................................................................... 656 25.11 Direct Transitions.............................................................................................................. 656 25.12 Usage Notes ...................................................................................................................... 657 25.12.1 I/O Port Status...................................................................................................... 657 25.12.2 Current Consumption when Waiting for Oscillation Stabilization ...................... 657 25.12.3 DTC Module Stop Mode ..................................................................................... 657 Section 26 List ...
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Index .......................................................................................................................................... 783 Rev. 3.00 Mar 21, 2006 page xxxvii of liv ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B.................................................................................................... Figure 1.2 Internal Block Diagram of H8S/2160B and H8S/2161B ..................................... Figure 1.3 Pin Arrangement of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B ..... Figure 1.4 Pin Arrangement of ...
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Figure 4.3 Operation when SP Value Is Odd ........................................................................ 87 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ................................................................ 90 Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, Interrupts WUE7 to WUE0, and ...
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Figure 7.4 DTC Operation Flowchart ................................................................................... 155 Figure 7.5 Memory Mapping in Normal Mode..................................................................... 156 Figure 7.6 Memory Mapping in Repeat Mode...................................................................... 157 Figure 7.7 Memory Mapping in Block Transfer Mode ......................................................... 158 Figure 7.8 Chain Transfer Operation .................................................................................... 159 ...
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Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) ............................................. 282 Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used) .................................................... 283 Section 12 8-Bit Timer (TMR) Figure 12.1 ...
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Output Timing of RESO signal............................................................................ 355 Figure 14.5 Figure 14.6 Writing to TCNT and TCSR (WDT_0) ............................................................... 356 Figure 14.7 Conflict between TCNT Write and Increment..................................................... 357 Sample Circuit for Resetting System by RESO Signal........................................ 358 Figure 14.8 Section 15 ...
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Figure 15.27 Sample Flowchart for Mode Transition during Reception................................... 410 Figure 15.28 Switching from SCK Pins to Port Pins ................................................................ 411 Figure 15.29 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ........ 411 2 Section ...
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Figure 16.28 IRIC Setting Timing and SCL Control (3)........................................................... 470 Figure 16.29 Block Diagram of Noise Canceler ....................................................................... 473 Figure 16.30 Notes on Reading Master Receive Data............................................................... 479 Figure 16.31 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing........................................................................................................... ...
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Figure 19.5 Power-Down State Termination Timing.............................................................. 571 Figure 19.6 SERIRQ Timing................................................................................................... 572 Figure 19.7 Clock Start Request Timing................................................................................. 574 Figure 19.8 HIRQ Flowchart (Example of Channel 1) ........................................................... 577 Section 20 D/A Converter Figure 20.1 Block Diagram of D/A Converter ...
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Figure 24.5 External Clock Input Timing ............................................................................... 636 Figure 24.6 Timing of External Clock Output Stabilization Delay Time ............................... 637 Figure 24.7 Subclock Input Timing ........................................................................................ 638 Figure 24.8 Processing for X1 and X2 Pins ............................................................................ 640 Figure 24.9 Note ...
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Figure 27. Bus Interface Input/Output Timing................................................................ 775 Figure 27.30 Host Interface (LPC) Timing ............................................................................... 775 Figure 27.31 Tester Measurement Condition............................................................................ 776 Appendix C Package Dimensions Figure C.1 Package Dimensions (FP-100B) .......................................................................... 780 Figure C.2 Package Dimensions (TFP-100B)........................................................................ ...
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Section 1 Overview Table 1.1 Pin Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B in Each Operating Mode ........................................................................................ Table 1.2 Pin Functions of H8S/2160B and H8S/2161B in Each Operating Mode ............... 12 Table 1.3 Pin Functions.......................................................................................................... 18 Section 2 CPU ...
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Table 5.5 Interrupt Response Times....................................................................................... 112 Table 5.6 Number of States in Interrupt Handling Routine Execution Status........................ 112 Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration ................................................................................................... 123 Table 6.2 Bus Specifications for Basic Bus Interface ............................................................ 127 Address ...
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Table 10.4 Position of Pulse to Be Added to Basic Pulse (CFS = 1) ....................................... 256 Section 11 16-Bit Free-Running Timer (FRT) Table 11.1 Pin Configuration ................................................................................................... 261 Table 11.2 FRT Interrupt Sources............................................................................................ 279 Table 11.3 Switching of Internal Clock ...
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Table 15.9 SSR Status Flags and Receive Data Handling........................................................ 384 Table 15.10 IrCKS2 to IrCKS0 Bit Settings .............................................................................. 404 Table 15.11 SCI Interrupt Sources ............................................................................................. 405 2 Section Bus Interface (IIC) (Optional) Table 16.1 Pin Configuration ................................................................................................... ...
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Section 20 D/A Converter Table 20.1 Pin Configuration ................................................................................................... 580 Table 20.2 D/A Channel Enable............................................................................................... 582 Section 21 A/D Converter Table 21.1 Pin Configuration ................................................................................................... 587 Table 21.2 Analog Input Channels and Corresponding ADDR Registers................................ 588 Table 21.3 A/D Conversion ...
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Table 27.8 Timing of On-Chip Peripheral Modules (2) ........................................................... 716 Table 27.9 Keyboard Buffer Controller Timing....................................................................... 717 2 Table 27. Bus Timing....................................................................................................... 717 Table 27.11 LPC Module Timing .............................................................................................. 718 Table 27.12 A/D Conversion Characteristics (AN7 to AN0 ...
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Rev. 3.00 Mar 21, 2006 page liv of liv ...
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Features High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions Various peripheral functions Data transfer controller (DTC) 8-bit PWM timer (PWM) ...
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Section 1 Overview On-chip memory ROM Model HD64F2161BV * F-ZTAT Version HD64F2160BV * HD64F2141BV * HD64F2140BV * HD64F2145BV * HD64F2145B HD64F2148BV * HD64F2148B Note: * 3-V version product General I/O ports I/O pins: 74 (H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B) I/O ...
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Block Diagram RES XTAL EXTAL VCCB MD1 MD0 NMI STBY RESO P97/WAIT/SDA0 P96/ /EXCL P95/AS/IOS/CS1 P94/HWR/IOW P93/RD/IOR P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG/ECS2 P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD P52/SCK0/SCL0 P51/RxD0 P50/TxD0 ...
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Section 1 Overview X1 X2 RES XTAL EXTAL VCCB MD1 MD0 NMI STBY RESO P97/WAIT/SDA0 P96/ /EXCL P95/AS/IOS/CS1 P94/HWR/IOW P93/RD/IOR P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG/ECS2 P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD P52/SCK0/SCL0 ...
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Pin Arrangement and Functions 1.3.1 Pin Arrangement P13/A3/PW3 77 P12/A2/PW2 78 P11/A1/PW1 79 P10/A0/PW0 PB3/D3/WUE3 * /CS4 80 ...
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Section 1 Overview 108 107 106 105 104 103 102 101 100 P12/A2/PW2 109 P11/A1/PW1 110 VSS 111 P10/A0/PW0 112 PB7/D7/WUE7 113 PB6/D6/WUE6 114 PB5/D5/WUE5 115 PB4/D4/WUE4 116 PB3/D3/WUE3/CS4 ...
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Pin Functions in Each Operating Mode Table 1.1 Pin Functions of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B in Each Operating Mode Pin No. Extended Modes FP-100B TFP-100B Mode 1 RES 1 2 XTAL 3 EXTAL 4 VCCB 5 MD1 6 ...
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Section 1 Overview Pin No. Extended Modes FP-100B TFP-100B Mode P92/IRQ0 24 P91/IRQ1 25 P90/LWR/IRQ2/ ADTRG 26 P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX 27 P61/FTOA/CIN1/ KIN1/VSYNCO 28 P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY 29 P63/FTIB/CIN3/ KIN3/VFBACKI 30 (B) PA3/CIN11/KIN11/ PS2AD 31 (B) PA2/CIN10/KIN10/ ...
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Pin No. Extended Modes FP-100B TFP-100B Mode 1 42 P74/AN4 43 P75/AN5 44 P76/AN6/DA0 45 P77/AN7/DA1 46 AVSS 47 (B) PA1/CIN9/KIN9 48 (B) PA0/CIN8/KIN8 49 P40/TMCI0/TxD2/ IrTxD 50 P41/TMO0/RxD2/ IrRxD 51 (N) P42/TMRI0/SCK2/ SDA1 52 P43/TMCI1/ HSYNCI 53 P44/TMO1/ HSYNCO ...
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Section 1 Overview Pin No. Extended Modes FP-100B TFP-100B Mode 1 65 A10 PB5/D5/WUE5 * 68 PB4/D4/WUE4 * 69 70 VSS 71 VSS ...
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Pin No. Extended Modes FP-100B TFP-100B Mode 1 PB0/D0/WUE0 * 91 92 VSS 93 P80 94 P81 95 P82 96 P83 97 P84/IRQ3/TxD1 98 P85/IRQ4/RxD1 99 (N) P86/IRQ5/SCK1/ SCL1 RESO 100 Notes: The (B) in Pin No. means the VCCB ...
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Section 1 Overview Table 1.2 Pin Functions of H8S/2160B and H8S/2161B in Each Operating Mode Pin No. Extended modes TFP-144 Mode 1 1 VCC 2 P43/TMCI1/ HSYNCI 3 P44/TMO1/ HSYNCO 4 P45/TMRI1/ CSYNCI 5 P46/PWX0 6 P47/PWX1 7 VSS RES ...
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Pin No. Extended modes TFP-144 Mode 1 25 PE7 26 PE6 27 PE5 28 PE4 29 PE3 30 PE2 31 PE1 32 PE0 33 (B) PA7/CIN15/KIN15/ PS2CD 34 (B) PA6/CIN14/KIN14/ PS2CC 35 (B) PA5/CIN13/KIN13/ PS2BD 36 VCCB 37 (B) PA4/CIN12/KIN12/ ...
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Section 1 Overview Pin No. Extended modes TFP-144 Mode 1 49 PF1 50 PF0 51 (N) PG7 52 (N) PG6 53 (N) PG5 54 (N) PG4 55 (N) PG3 56 (N) PG2 57 (N) PG1 58 (N) PG0 59 PD7 ...
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Pin No. Extended modes TFP-144 Mode 1 77 AVref 78 P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX 79 P61/FTOA/CIN1/ KIN1/VSYNCO 80 P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY 81 P63/FTIB/CIN3/ KIN3/VFBACKI 82 P64/FTIC/CIN4/ KIN4/CLAMPO 83 P65/FTID/CIN5/ KIN5 84 P66/FTOB/CIN6/ KIN6/IRQ6 85 P67/TMOX/CIN7/ KIN7/IRQ7 86 VCC 87 PC7 88 PC6 ...
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Section 1 Overview Pin No. Extended modes TFP-144 Mode 1 98 A13 99 A12 100 A11 101 A10 102 A9 103 A8 104 A7 105 A6 106 A5 107 A4 108 A3 109 A2 110 A1 111 VSS 112 A0 ...
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Pin No. Extended modes TFP-144 Mode 1 125 D12 126 D13 127 D14 128 D15 129 P80 130 P81 131 P82 132 P83 133 P84/IRQ3/TxD1 134 P85/IRQ4/RxD1 135 (N) P86/IRQ5/SCK1/ SCL1 136 P40/TMCI0/TxD2/ IrTxD 137 P41/TMO0/RxD2/ IrRxD 138 (N) P42/TMRI0/SCK2/ ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 Pin Functions FP-100B, Type Symbol TFP-100B TFP-144 I/O Power VCC 59 VCL 9 VCCB 4 VSS 15, 70, 71, 92 Clock XTAL 2 EXTAL 3 17 EXCL 17 X1 — X2 — ...
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FP-100B, Type Symbol TFP-100B TFP-144 I/O Address A23 to 10, 11, 20, bus A16 21, 30, 31, 47, 48 A15 67 Data bus D15 57, ...
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Section 1 Overview FP-100B, Type Symbol TFP-100B TFP-144 I/O 16-bit free- FTCI 26 running FTOA 27 timer (FRT) FTOB 34 FTIA 28 FTIB 29 FTIC 32 FTID 33 8-bit timer TMO0 50 (TMR_0, TMO1 53 TMR_1, TMOX 35 TMR_X) TMCI0 ...
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FP-100B, Type Symbol TFP-100B TFP-144 I/O Keyboard PS2AC 31 buffer PS2BC 21 controller PS2CC 11 PS2AD 30 PS2BD 20 PS2CD 10 Host HDB7 interface HDB0 (XBS) CS1, 18, 94, CS2/ 25, 81, 80 ECS2, CS3, CS4 ...
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Section 1 Overview FP-100B, Type Symbol TFP-100B TFP-144 I/O Host SERIRQ 89 interface (LPC) LSCI, 90, 91, 93 LSMI, PME GA20 94 CLKRUN 95 LPCPD 96 KIN0 to Keyboard 26 to 29, KIN15 buffer 32 to 35, controller 48, 47, ...
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FP-100B, Type Symbol TFP-100B TFP-144 I/O A/D AVCC 37 converter D/A converter AVref 36 AVSS 46 Timer VSYNCI 28 connection HSYNCI 52 CSYNCI 54 VFBACKI 29 HFBACKI 26 VSYNCO 27 HSYNCO 53 CLAMPO 32 CBLANK bus ...
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Section 1 Overview FP-100B, Type Symbol TFP-100B TFP-144 I/O I/O ports P52 P50 P67 P60 P77 P70 P86 P80 P97 to ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU 16 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 16-bit register-register divide: 20 states (DIVXU.W) Two CPU operating modes Normal mode Advanced mode Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. Expanded address space Normal ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's ...
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H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Figure 2.1 Exception Vector Table (Normal Mode (16 bits) (a) Subroutine Branch Note: * Ignored when returning. Figure 2.2 Stack Structure in Normal Mode 2.2.2 Advanced ...
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Section 2 CPU Instruction set All instructions and addressing modes can be used. Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. ...
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Stack structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and ...
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Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Section 2 CPU Bit Bit Name Initial Value Undefined 5 H Undefined 4 U Undefined 3 N Undefined 2 Z Undefined 1 V Undefined 0 C Undefined Rev. 3.00 Mar 21, 2006 page 36 of ...
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Initial Register Values The program counter (PC) among CPU internal registers is initialized when reset exception handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the interrupt mask ...
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Section 2 CPU Data Type General Register Word data Rn Word data En 15 MSB Longword data ERn 31 MSB Legend: ERn : General register General register General register R RnH : General register ...
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Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made ...
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Section 2 CPU 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * 1 , PUSH * ...
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Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination ...
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Section 2 CPU Table 2.3 Data Transfer Instructions Size * 1 Instruction Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot ...
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Table 2.4 Arithmetic Operations Instructions (1) Instruction Size * Function ADD B/W/L Rd SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Subtraction on immediate data and data ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size * 1 Function DIVXS B/W Rd Performs signed division on data in two general registers: either 16 bits 8 bits quotient and 16-bit remainder. CMP B/W/L Rd – Rs, ...
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Table 2.5 Logic Operations Instructions Instruction Size * Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on a general register ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size * Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Table 2.7 Bit Manipulation Instructions (2) Size * Instruction Function BXOR B C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ...
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Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) ...
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Table 2.9 System Control Instructions Size * Instruction Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the memory operand contents or ...
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Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next; EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number ...
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Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective ...
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Section 2 CPU Table 2.11 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory ...
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Register Indirect with Pre-Decrement—@–ERn: The value subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also ...
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Section 2 CPU 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the ...
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Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address ...
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Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Rev. 3.00 Mar 21, 2006 page 56 of 788 REJ09B0300-0300 Effective Address Calculation Operand is immediate data. PC contents Sign extension Memory contents ...
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Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. Reset state In this state the CPU and ...
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Section 2 CPU End of bus request Bus-released state End of exception handling Exception-handling state RES = high Reset state * 1 From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. ...
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Usage Notes 2.9.1 Note on TAS Instruction Usage When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. When the TAS ...
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Section 2 CPU Prior to executing BCLR: P47 P46 Input/output Input Input Pin state Low High level level DDR BCLR instruction executed: BCLR #0, @P4DDR After executing BCLR: P47 P46 Input/output Output Output Pin state ...
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EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6 R4L 2. Set R4L ...
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Section 2 CPU Rev. 3.00 Mar 21, 2006 page 62 of 788 REJ09B0300-0300 ...
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Section 3 MCU Operating Modes 3.1 MCU Operating Mode Selection This LSI has three operating modes (modes 1 to 3). The operating mode is determined by the setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU ...
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Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit Bit Name Initial Value 7 EXPE —* 6 — All ...
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System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, pin location selection, enables or disables register access to the on-chip peripheral modules, and ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 2 NMIEG 0 1 HIE 0 0 RAME 1 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects ...
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Bit Bit Name Initial Value 7 IICS 0 6 IICX1 0 5 IICX0 0 4 IICE 0 Section 3 MCU Operating Modes R/W Description 2 R Extra Buffer Select Specifies bits port A as ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 3 FLSHE 0 2 — ICKS1 0 0 ICKS0 0 Rev. 3.00 Mar 21, 2006 page 68 of 788 REJ09B0300-0300 R/W Description R/W Flash Memory Control Register Enable ...
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Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled. Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and ...
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Section 3 MCU Operating Modes 3.3.4 Pin Functions in Each Operating Mode Pin functions of ports and B depend on the operating mode. Table 3.2 shows pin functions in each operating mode. Table 3.2 Pin ...
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Address Map in Each Operating Mode Figures 3.1 to 3.10 show the address map in each operating mode. Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 External address space H'E080 On-chip RAM * H'EFFF H'F000 External ...
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Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'DFFF External address H'E080 H'EFFF External address H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Note: * These areas ...
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Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 External address space H'E080 On-chip RAM * H'EFFF H'F000 External address space H'F7FF H'F800 Internal I/O registers 3 H'FE4F H'FE50 Internal I/O H'FEFF registers 2 H'FF00 On-chip RAM (128 ...
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Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'DFFF External address H'E080 H'EFFF H'F000 External address H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Note: * These areas ...
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Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 External address space H'E080 On-chip RAM * H'EFFF H'F000 External address space H'F7FF H'F800 Internal I/O registers 3 H'FE4F H'FE50 Internal I/O registers 2 H'FEFF H'FF00 On-chip RAM (128 ...
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Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'DFFF External address H'E080 H'EFFF H'F000 External address H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Note: * These areas ...
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Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 External address space H'E080 On-chip RAM * H'EFFF External address H'F000 space H'F7FF H'F800 Reserved area H'FE4F H'FE50 Internal I/O registers 2 H'FEFF H'FF00 On-chip RAM (128 bytes) * ...
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Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'DFFF External address H'E080 H'EFFF External address H'F000 H'F7FF H'F800 Reserved area H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Note: * ...
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Mode 1 Normal mode Extended mode with on-chip ROM disabled H'0000 External address space H'E080 On-chip RAM * H'EFFF External address H'F000 space H'F7FF H'F800 Reserved area H'FE4F H'FE50 Internal I/O registers 2 H'FEFF H'FF00 On-chip RAM (128 bytes) * ...
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Section 3 MCU Operating Modes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM enabled H'0000 H'DFFF External address H'E080 H'EFFF External address H'F000 H'F7FF H'F800 Reserved area H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Note: * ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Exception Source Reset Reserved ...
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Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ...
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Section 4 Exception Handling RES Internal address bus Internal read signal Internal write signal Internal data bus (1) Reset exception handling vector address ((1) = H'0000) (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) ...
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Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to WUE0) and internal interrupt sources from the on-chip ...
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Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode SP (16 bits) Note: * Ignored on return. Figure 4.2 Stack Status ...
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Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should ...
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Section 4 Exception Handling Rev. 3.00 Mar 21, 2006 page 88 of 788 REJ09B0300-0300 ...
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Section 5 Interrupt Controller 5.1 Features Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). Priorities settable with ICR An interrupt control ...
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Section 5 Interrupt Controller SYSCR NMIEG NMI input IRQ input KIN input WUE input Internal interrupt request SWDTEND to IBF13 Interrupt controller Legend: ICR : Interrupt control register : IRQ sense control register ISCR : IRQ enable register IER : ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol I/O NMI Input IRQ7 to IRQ0 Input KIN15 to KIN0 Input WUE7 to WUE0 * Input Note: * Not supported by the H8S/2148B ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers (ICRA to ICRC) The ICR registers set interrupt control levels for interrupts other than NMI and address breaks. The correspondence between interrupt sources and ICRA to ICRC settings is ...
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Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set address break is requested. Bit Bit Name Initial Value 7 CMF 0 6 — All 0 ...
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Section 5 Interrupt Controller 5.3.3 Break Address Registers (BARA to BARC) The BAR registers specify an address that break address. An address in which the first byte of an instruction exists should be ...
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IRQ Sense Control Registers (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0. ISCRH Bit Bit Name Initial Value 7 IRQ7SCB 0 6 IRQ7SCA 0 5 IRQ6SCB 0 4 IRQ6SCA ...
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Section 5 Interrupt Controller 5.3.5 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit Name Initial Value 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E ...
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Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Interrupt Mask Register (WUEMRB) The KMIMRA, KMIMR, and WUEMRB registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0), and wake-up event interrupt inputs (WUE7 to WUE0). KMIMRA Bit ...
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Section 5 Interrupt Controller WUEMRB * Bit Bit Name Initial Value 7 WUEMR7 1 6 WUEMR6 1 5 WUEMR5 1 4 WUEMR4 1 3 WUEMR3 1 2 WUEMR2 1 1 WUEMR1 1 0 WUEMR0 1 Note: * Not supported by ...
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KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 KMIMR8 (initial value 1) PA0/KIN8 KMIMR9 (initial value 1) PA1/KIN9 WUEMR7 (initial value 1) PB7/WUE7 Figure 5.2 Relationship between Interrupts ...
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Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, ...
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IRQnSCA, IRQnSCB detection circuit IRQn input Note Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0. When pin ...
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Section 5 Interrupt Controller 5.4.2 Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following features: 1. For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select ...
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Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source Name External NMI pin IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8, WUE7 to WUE0 DTC SWDTEND (Software activation data transfer ...
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Section 5 Interrupt Controller Origin of Interrupt Source Name TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use TMR_X, CMIAY (Compare match A) TMR_Y CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture X) ...
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Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted ...
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Section 5 Interrupt Controller 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt and starts execution ...
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Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR ...
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Section 5 Interrupt Controller Figure 5.6 shows a flowchart of the interrupt acceptance operation interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. 2. ...
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Program excution state Interrupt generated? Yes An interrupt with interrupt control level 1? Yes No IRQ0 No Yes IRQ1 Yes IFBFI3 Yes Yes Yes Save PC and CCR I Read vector address Branch ...
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Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...
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Figure 5.7 Interrupt Exception Handling Section 5 Interrupt Controller Rev. 3.00 Mar 21, 2006 page 111 of 788 REJ09B0300-0300 ...
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Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.5 shows interrupt response times and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.5 are explained in table 5.6. Table 5.5 ...
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DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: Interrupt request to CPU Activation request to DTC Selection of a number of the above For details on interrupt ...
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Section 5 Interrupt Controller Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See table 7.1 for the respective priority. Operation Order: If the ...
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Address Break 5.7.1 Features This LSI can determine the specific address prefetch by the CPU to generate an address break interrupt by setting ABRKCR and BAR address break interrupt is generated, the address break interrupt exception handling ...
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Section 5 Interrupt Controller 5.7.3 Operation If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address break interrupt can be generated. This address break function generates an interrupt request to the interrupt controller at ...
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When a break address specified instruction is executed for one state in the program area and on-chip memory Instruction Instruction Instruction fetch fetch fetch H'0310 H'0312 H'0314 H'0316 Address bus NOP NOP execution execution Break request signal H'0310 NOP ...
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Section 5 Interrupt Controller 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable ...
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Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit ...
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Section 5 Interrupt Controller 5.8.5 IRQ Status Register (ISR) According to the pin status after a reset, IRQnF may be set ISR should be read after a reset to write Rev. ...
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Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. The BSC also has a bus arbitration function, and controls the ...
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Section 6 Bus Controller (BSC) External bus control signals WAIT Figure 6.1 Block Diagram of Bus Controller Rev. 3.00 Mar 21, 2006 page 122 of 788 REJ09B0300-0300 Bus controller BCR WSCR Wait controller CPU bus request signal DTC bus request ...
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Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Pin Configuration Symbol I/O AS Output IOS Output RD Output HWR Output LWR Output WAIT Input 6.3 Register Descriptions The bus controller has the following registers. ...
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Section 6 Bus Controller (BSC) 6.3.1 Bus Control Register (BCR) BCR is used to specify the access mode for the external address space or the I/O area range when the AS/IOS pin is specified as an I/O strobe pin. Bit ...
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Wait State Control Register (WSCR) WSCR is used to specify the data bus width for external address space access, the number of access states, the wait mode, and the number of wait states for access to external address spaces. ...
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value 1 WC1 1 0 WC0 1 6.4 Bus Control 6.4.1 Bus Specifications The external address space bus specifications consist of three elements: Bus width, the number of access states, and ...
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Table 6.2 shows the bus specifications for the basic bus interface of each area. Table 6.2 Bus Specifications for Basic Bus Interface ABW AST WMS1 WMS0 0 0 — — —* — — — 1 ...
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Section 6 Bus Controller (BSC) RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the RAME bit is cleared to 0. 6.4.4 I/O Select Signals The LSI can output I/O select ...
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Basic Bus Interface The basic bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications when using the basic bus interface, see table 6.2 6.5.1 Data Size and Data Alignment Data sizes ...
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Section 6 Bus Controller (BSC) Byte size • Even address Byte size • Odd address Word size Longword 1st bus cycle size 2nd bus cycle Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes Table ...
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Basic Operation Timing 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait ...
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Section 6 Bus Controller (BSC) 8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. ...
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Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and ...
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Section 6 Bus Controller (BSC) Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) D15 to D8 Read Write D15 Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte ...
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Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD D15 to D8 Read HWR LWR Write D15 Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Section 6 ...
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Section 6 Bus Controller (BSC) 16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is ...
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Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD D15 to D8 Read HWR LWR Write D15 Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) Section ...
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Section 6 Bus Controller (BSC) Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD D15 to D8 Read HWR LWR Write D15 Figure 6.12 Bus Timing for 16-Bit, 3-State Access ...
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Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait states (T ). There are three ways of inserting wait states: Program wait insertion, pin W wait insertion ...
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Section 6 Bus Controller (BSC) WAIT Address bus AS/IOS (IOSE = 0) RD Read Data bus HWR, LWR Write Data bus Note: ↓ shown in clock indicates the WAIT pin sampling timing. Figure 6.13 Example of Wait State Insertion Timing ...
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Burst ROM Interface In this LSI, the external address space can be designated as the burst ROM space by setting the BRSTRM bit in BCR to 1, and the burst ROM interface enabled. Consecutive burst accesses of a maximum ...
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Section 6 Bus Controller (BSC) Address bus AS/IOS (IOSE = 0) RD Data bus Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control As with the basic bus interface, program wait insertion ...
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Bus cycle Address bus RD HWR, LWR Data bus Long output floating time (a) No idle cycle insertion Figure 6.16 Examples of Idle Cycle Operation Table 6.5 shows the pin states in an idle cycle. ...
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Section 6 Bus Controller (BSC) 6.8 Bus Arbitration The bus controller has a bus arbiter that arbitrates bus master operations. There are two bus masters – the CPU and DTC – that perform read/write operations when they have possession of ...