DF2144AFA20V Renesas Electronics America, DF2144AFA20V Datasheet
DF2144AFA20V
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DF2144AFA20V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2148 Group, H8S/2144 Group, H8S/2148F-ZTAT™, H8S/2147N F-ZTAT™, 16 H8S/2144F-ZTAT™, H8S/2142F-ZTAT™ Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series H8S/2148 HD6432148S H8S/2147 HD6432147S The revision list can be viewed directly by clicking the title page. The revision list summarizes the ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Rev. 4.00 Sep 27, 2006 page iv of xliv ...
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The H8S/2148 Group, H8S/2144 Group, and H8S/2147N comprise high-performance microcomputers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided ...
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This manual describes the hardware of the H8S/2148 Group, H8S/2144 Group, and H8S/2147N. Refer to the H8S/2600 Series and H8S/2000 Series Software Manual for a detailed description of the instruction set. Note: * F-ZTAT (Flexible-ZTAT trademark of Renesas ...
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Main Revisions for This Edition Item Page All — 1.1 Overview 4 Table 1.1 Overview 6 1.2 Internal Block 7 Diagram Figure 1.1 (a) Internal Block Diagram of H8S/2148 Group Figure 1.1 (b) Internal 8 Block Diagram of H8S/2147N Revision ...
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Item Page 1.3.2 Pin Functions in 14 Each Operating Mode Table 1.2 (a) Pin Functions in Each 17 Operating Mode Table 1.2 (b) 19 H8S/2147N Pin Functions in Each 21 Operating Mode 1.3.3 Pin Functions 30 Table 1.3 Pin Functions ...
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Item Page 5.2.8 Address Break 124 Control Register (ABRKCR) 5.5.3 Interrupt control 140 Mode 1 Figure 5.9 Example of State Transitions in Interrupt control Mode 1 8.1 Overview 213 Table 8.1 H8S/2148 Group Port Functions Table 8.2 H8S/2147N 216 Port ...
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Item Page 8.1 Overview 220 Table 8.3 H8S/2144 Port Functions 8.7.2 Register 247 Configuration Table 8.14 Port 6 Registers 8.9.3 Pin Functions 258 Table 8.19 Port 8 Pin Functions Rev. 4.00 Sep 27, 2006 page x of xliv Revision (See ...
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Item Page 8.11.3 Pin Functions 270 Table 8.23 Port A Pin Functions 9.3.1 Correspondence 289 between PWM Data Register Contents and Output Waveform Table 9.4 Duty Cycle of Basic Pulse 10.3 Bus Master 299 Interface 10.4 Operation 303 Table 10.4 ...
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Item Page 16.1.1 Features 492 16.4 Usage Notes 548 Figure 16.19 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission 550 to 557 20.4.3 Input Sampling 628 and A/D Conversion Time Figure 20.5 A/D Conversion Time Rev. 4.00 Sep ...
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Item Page 22.4.2 Block Diagram 643 Figure 22.2 Block Diagram of Flash Memory 22.5.3 Erase Block 653 Registers 1 and 2 (EBR1, EBR2) 22.10.1 Programmer 671 Mode Setting 22.10.4 Memory Read 675 Mode Figure 22.17 Timing Waveforms when Entering Another ...
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Item Page 22.10.4 Memory Read 676 Mode Figure 22.19 Timing Waveforms for CE/OE Clocked Read 22.10.7 Status Read 681 Mode Figure 22.22 Status Read Mode Timing Waveforms 23.5.3 Erase Block 699 Registers 1 and 2 (EBR1, EBR2) Table 23.5 Flash ...
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Item Page 23.6.1 Boot Mode 705 23.7.2 Program-Verify 710 Mode Figure 23.12 Program/Program-Verify Flowcharts 23.10.4 Memory Read 721 Mode Figure 23.17 Timing Waveforms when Entering Another Mode from Memory Read Mode Revision (See Manual for Details) Description amended H'(FF)E088 and ...
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Item Page 23.10.4 Memory Read 722 Mode Figure 23.19 Timing Waveforms for CE/OE Clocked Read 23.10.5 Auto-Program 724 Mode Figure 23.20 Auto- Program Mode Timing Waveforms 23.10.6 Auto-Erase 725 Mode Figure 23.21 Auto- Erase Mode Timing Waveforms Rev. 4.00 Sep ...
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Item Page 23.10.7 Status Read 727 Mode Figure 23.22 Status Read Mode Timing Waveforms 24.7 Subclock Input 740 Circuit 25.12 Usage Notes 764 26.2.6 Flash Memory 799 Characteristics Table 26.15 Flash Memory Characteristics (Programming/erasing operating range) 800 26.3.3 AC 819 ...
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Item Page 26.3.4 A/D Conversion 831 Characteristics Table 26.27 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266- State Conversion) 26.3.6 Flash Memory 833 Characteristics Table 26.29 Flash Memory Characteristics (Programming/erasing operating range) 834 26.4.3 AC 849 Characteristics Table 26.35 Control ...
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Item Page 26.4.6 Flash Memory 862 Characteristics Table 26.43 Flash Memory Characteristics (Programming/erasing operating range) 863 26.5.3 AC 877 Characteristics Table 26.49 Control Signal Timing 26.5.6 Flash Memory 885 Characteristics Table 26.55 Flash Memory Characteristics (Programming/erasing 886 operating range) 26.6.3 ...
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Item Page 26.6.6 Flash Memory 908 Characteristics Table 26.67 Flash Memory Characteristics (Programming/erasing operating range) 909 26.7.2 Clock Timing 912 Figure 26.6 Oscillation Settling Timing 26.7.5 Timing of On- 924 Chip Supporting Modules 2 Figure 26. Bus Interface ...
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Item Page A.1 Instruction 930 Table A.1 Instruction Set 933 939 A.2 Instruction Codes 949 Table A.2 Instruction Codes Revision (See Manual for Details) Table A.1 amended 2. Arithmetic Instructions Addressing Mode and Instruction Length (Bytes) Mnemonic EXTU EXTU.W Rd ...
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Item Page B.3 Functions 1013 1016 1019 1021 Rev. 4.00 Sep 27, 2006 page xxii of xliv Revision (See Manual for Details) Subheading amended KBCOMP H'FEE4 IrDA/Expansion A/D ISR H'FEEB Interrupt Controller Figure amended IRQ7 to IRQ0 flags 0 [Clearing ...
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Item Page B.3 Functions 1025 1030 1059 Revision (See Manual for Details) EBR1 H'FF82 Flash Memory EBR2 H'FF83 Flash Memory Figure amended Read/Write description of bits (Before) Bit EBR1 — — — Initial value ...
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Item Page B.3 Functions 1077 1080 C.2 Port 2 Block 1089 Diagrams Figure C.4 Port 2 Block Diagram (Pin P27) Appendix F Product 1128 Code Lineup Table F.1 H8S/2148 Group and H8S/2144 Group Product Code Lineup Appendix G Package 1129 ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Internal Block Diagram..................................................................................................... 1.3 Pin Arrangement and Functions........................................................................................ 10 1.3.1 Pin Arrangement .................................................................................................. 10 1.3.2 Pin Functions in Each Operating Mode ............................................................... 13 1.3.3 Pin Functions ....................................................................................................... 26 Section 2 CPU ...................................................................................................................... 35 ...
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Bus-Released State............................................................................................... 76 2.8.6 Power-Down State ............................................................................................... 77 2.9 Basic Timing ..................................................................................................................... 78 2.9.1 Overview.............................................................................................................. 78 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 78 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 80 2.9.4 External Address Space Access Timing .............................................................. 81 ...
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Section 5 Interrupt Controller 5.1 Overview........................................................................................................................... 113 5.1.1 Features................................................................................................................ 113 5.1.2 Block Diagram ..................................................................................................... 114 5.1.3 Pin Configuration................................................................................................. 115 5.1.4 Register Configuration......................................................................................... 116 5.2 Register Descriptions ........................................................................................................ 117 5.2.1 System Control Register (SYSCR) ...................................................................... 117 5.2.2 Interrupt Control Registers A ...
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Section 6 Bus Controller 6.1 Overview........................................................................................................................... 151 6.1.1 Features................................................................................................................ 151 6.1.2 Block Diagram ..................................................................................................... 152 6.1.3 Pin Configuration................................................................................................. 153 6.1.4 Register Configuration......................................................................................... 153 6.2 Register Descriptions ........................................................................................................ 154 6.2.1 Bus Control Register (BCR) ................................................................................ 154 6.2.2 Wait State Control Register ...
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DTC Destination Address Register (DAR).......................................................... 185 7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 186 7.2.6 DTC Transfer Count Register B (CRB)............................................................... 186 7.2.7 DTC Enable Registers (DTCER) ......................................................................... 187 7.2.8 DTC Vector Register (DTVECR)........................................................................ 188 7.2.9 Module Stop ...
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Register Configuration......................................................................................... 238 8.5.3 Pin Functions ....................................................................................................... 239 8.6 Port 5................................................................................................................................. 243 8.6.1 Overview.............................................................................................................. 243 8.6.2 Register Configuration......................................................................................... 243 8.6.3 Pin Functions ....................................................................................................... 245 8.7 Port 6................................................................................................................................. 246 8.7.1 Overview.............................................................................................................. 246 8.7.2 Register Configuration......................................................................................... 247 8.7.3 Pin Functions ....................................................................................................... ...
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PWM Register Select (PWSL)............................................................................. 282 9.2.2 PWM Data Registers (PWDR0 to PWDR15) ...................................................... 284 9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 284 9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 285 ...
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Timer Control/Status Register (TCSR) ................................................................ 316 11.2.8 Timer Control Register (TCR) ............................................................................. 319 11.2.9 Timer Output Compare Control Register (TOCR) .............................................. 321 11.2.10 Module Stop Control Register (MSTPCR) .......................................................... 324 11.3 Operation .......................................................................................................................... 325 11.3.1 FRC Increment Timing ........................................................................................ ...
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Compare-Match Timing....................................................................................... 363 12.3.3 TCNT External Reset Timing .............................................................................. 364 12.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 365 12.3.5 Operation with Cascaded Connection.................................................................. 365 12.3.6 Input Capture Operation ...................................................................................... 367 12.4 Interrupt Sources............................................................................................................... 369 12.5 8-Bit Timer Application ...
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Block Diagram ..................................................................................................... 408 14.1.3 Pin Configuration................................................................................................. 409 14.1.4 Register Configuration......................................................................................... 410 14.2 Register Descriptions ........................................................................................................ 410 14.2.1 Timer Counter (TCNT)........................................................................................ 410 14.2.2 Timer Control/Status Register (TCSR) ................................................................ 411 14.2.3 System Control Register (SYSCR) ...................................................................... 414 14.2.4 Notes on ...
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Operation .......................................................................................................................... 453 15.3.1 Overview.............................................................................................................. 453 15.3.2 Operation in Asynchronous Mode ....................................................................... 455 15.3.3 Multiprocessor Communication Function............................................................ 466 15.3.4 Operation in Synchronous Mode ......................................................................... 474 15.3.5 IrDA Operation .................................................................................................... 483 15.4 SCI Interrupts.................................................................................................................... 486 15.5 Usage Notes ...................................................................................................................... 487 ...
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Features................................................................................................................ 559 17.1.2 Block Diagram ..................................................................................................... 561 17.1.3 Input/Output Pins ................................................................................................. 562 17.1.4 Register Configuration......................................................................................... 562 17.2 Register Descriptions ........................................................................................................ 563 17.2.1 Keyboard Control Register H (KBCRH) ............................................................. 563 17.2.2 Keyboard Control Register L (KBCRL) .............................................................. 565 17.2.3 Keyboard ...
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HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................ 601 18.5 Usage Note........................................................................................................................ 603 Section 19 D/A Converter 19.1 Overview........................................................................................................................... 605 19.1.1 Features................................................................................................................ 605 19.1.2 Block Diagram ..................................................................................................... 606 19.1.3 Input and Output Pins .......................................................................................... 607 19.1.4 Register Configuration......................................................................................... 607 19.2 ...
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Operation .......................................................................................................................... 637 21.3.1 Expanded Mode (Modes (EXPE = 1)) ...................................................... 637 21.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) ................................................. 637 Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, ...
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Memory Read Mode ............................................................................................ 673 22.10.5 Auto-Program Mode ............................................................................................ 677 22.10.6 Auto-Erase Mode................................................................................................. 679 22.10.7 Status Read Mode ................................................................................................ 680 22.10.8 Status Polling ....................................................................................................... 681 22.10.9 Programmer Mode Transition Time .................................................................... 682 22.10.10 Notes on Memory Programming...................................................................... 683 22.11 ...
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Error Protection.................................................................................................... 714 23.9 Interrupt Handling when Programming/Erasing Flash Memory....................................... 716 23.10 Flash Memory Programmer Mode .................................................................................... 717 23.10.1 Programmer Mode Setting ................................................................................... 717 23.10.2 Socket Adapters and Memory Map ..................................................................... 718 23.10.3 Programmer Mode Operation .............................................................................. 718 23.10.4 ...
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Medium-Speed Mode........................................................................................................ 753 25.4 Sleep Mode ....................................................................................................................... 754 25.4.1 Sleep Mode .......................................................................................................... 754 25.4.2 Clearing Sleep Mode............................................................................................ 754 25.5 Module Stop Mode ........................................................................................................... 755 25.5.1 Module Stop Mode .............................................................................................. 755 25.5.2 Usage Note........................................................................................................... 756 25.6 Software Standby Mode.................................................................................................... 757 ...
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Electrical Characteristics of H8S/2148 F-ZTAT (A-mask version), H8S/2147 F-ZTAT (A-mask version), and Mask ROM Versions of H8S/2148 and H8S/2147.................................................................................................................... 802 26.3.1 Absolute Maximum Ratings ................................................................................ 802 26.3.2 DC Characteristics ............................................................................................... 804 26.3.3 AC Characteristics ............................................................................................... 818 26.3.4 A/D Conversion ...
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Timing of On-Chip Supporting Modules............................................................. 919 Appendix A Instruction Set A.1 Instruction ......................................................................................................................... 925 A.2 Instruction Codes .............................................................................................................. 943 A.3 Operation Code Map......................................................................................................... 957 A.4 Number of States Required for Execution ........................................................................ 961 A.5 Bus States during Instruction Execution ...
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Rev. 4.00 Sep 27, 2006 page xliv of xliv ...
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Overview This LSI comprise microcomputers (MCUs) built around the H8S/2000 CPU, employing Renesas Technology proprietary architecture, and equipped with supporting modules on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a ...
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Section 1 Overview Table 1.1 Overview Item Specifications CPU General-register architecture High-speed operation suitable for real-time control Instruction set suitable for high-speed operation Two CPU operating modes Three MCU operating modes Operating modes Mode Rev. 4.00 Sep ...
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Item Specifications Bus controller 2-state or 3-state access space can be designated for external expansion areas Number of program wait states can be set for external expansion areas Data transfer Can be activated by internal interrupt or software controller (DTC) ...
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Section 1 Overview Item Specifications 14-bit PWM timer outputs (PWMX) Resolution: 1/16384 312.5 kHz maximum carrier frequency (20-MHz operation) Serial communication Asynchronous mode or synchronous mode selectable interface Multiprocessor communication function (SCI: 2 channels, SCI0 and SCI1) ...
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Item Specifications D/A converter Resolution: 8 bits Output: 2 channels I/O ports 74 input/output pins (including 24 with LED drive capability) 8 input-only pins VCCB (separate power supply) drive pins among I/O pins (H8S/2148 Group and H8S/2147N) Memory Flash memory ...
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Section 1 Overview Item Specifications Product lineup (preliminary) Group H8S/2148 H8S/2147N H8S/2144 Notes indicates the I Rev. 4.00 Sep 27, 2006 page 6 of 1130 REJ09B0327-0400 Product Code * 2 Mask ROM F-ZTAT Versions Versions HD6432148S HD64F2148 HD64F2148V ...
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Internal Block Diagram An internal block diagram of the H8S/2148 Group is shown in figure 1.1 (a), an internal block diagram of the H8S/2147N is shown in figure 1.1 (b), and an internal block diagram of the H8S/2144 Group ...
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Section 1 Overview RES XTAL EXTAL VCCB MD1 MD0 NMI STBY RESO P97/WAIT/SDA0 P96/ /EXCL P95/AS/IOS/CS1 P94/HWR/IOW P93/RD/IOR P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG/ECS2 P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0 P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12 P44/TMO1/HIRQ1 P43/TMCI1/HIRQ11 P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD P52/SCK0/SCL0 P51/RxD0 P50/TxD0 ...
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RES XTAL EXTAL MD1 MD0 NMI STBY RESO P97/WAIT P96/ /EXCL P95/AS/IOS P94/HWR P93/RD P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0 P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD P52/SCK0 P51/RxD0 P50/TxD0 Figure 1.1 (c) Internal ...
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Section 1 Overview 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement The pin arrangement of the H8S/2148 Group is shown in figure 1.2 (a), the pin arrangement of the H8S/2147N is shown in figure 1.2 (b), and the pin arrangement ...
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PW3/A3/P13 76 PW2/A2/P12 77 PW1/A1/P11 78 PW0/A0/P10 79 CS4/D3/PB3 80 CS3/D2/PB2 81 HDB0/D8/P30 82 HDB1/D9/P31 ...
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Section 1 Overview A3/P13 76 A2/P12 77 A1/P11 78 A0/P10 79 D3/PB3 80 D2/PB2 81 ...
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Pin Functions in Each Operating Mode Tables 1.2 (a), (b) and (c) show the pin functions of the H8S/2148 Group, H8S/2147N, and H8S/2144 Group in each of the operating modes. Table 1.2 (a) H8S/2148 Group Pin Functions in Each ...
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Section 1 Overview Pin No. Expanded Modes FP-100B TFP-100B Mode P92/IRQ0 24 P91/IRQ1 LWR/P90/IRQ2/ 25 ADTRG 26 P60/FTCI/CIN0/ KIN0/TMIX/ HFBACKI 27 P61/FTOA/CIN1/ KIN1/VSYNCO 28 P62/FTIA/CIN2/ KIN2/TMIY/ VSYNCI 29 P63/FTIB/CIN3/ KIN3/VFBACKI 30 PA3/CIN11/ KIN11/PS2AD 31 PA2/CIN10/ KIN10/PS2AC ...
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Pin No. Expanded Modes FP-100B TFP-100B Mode 1 42 P74/AN4 43 P75/AN5 44 P76/AN6/DA0 45 P77/AN7/DA1 46 AVSS 47 PA1/CIN9/KIN9 48 PA0/CIN8/KIN8 49 P40/TMCI0/ TxD2/IrTxD 50 P41/TMO0/ RxD2/IrRxD 51 P42/TMRI0/ SCK2/SDA1 52 P43/TMCI1/ HSYNCI 53 P44/TMO1/ HSYNCO 54 P45/TMRI1/ CSYNCI ...
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Section 1 Overview Pin No. Expanded Modes FP-100B TFP-100B Mode 1 65 A10 PB5/D5 69 PB4/D4 70 VSS 71 VSS ...
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Pin No. Expanded Modes FP-100B TFP-100B Mode 1 94 P81 95 P82 96 P83 97 P84/IRQ3/TxD1 98 P85/IRQ4/RxD1 99 P86/IRQ5/SCK1/ SCL1 RESO 100 Pin Name Single-Chip Modes Mode 2 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE ...
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Section 1 Overview Table 1.2 (b) H8S/2147N Pin Functions in Each Operating Mode Pin No. Expanded Modes FP-100B TFP-100B Mode 1 RES 1 2 XTAL 3 EXTAL 4 VCCB 5 MD1 6 MD0 7 NMI STBY 8 9 VCC2 10 ...
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Pin No. Expanded Modes FP-100B TFP-100B Mode 1 LWR/P90/IRQ2/ 25 ADTRG 26 P60/FTCI/CIN0/ KIN0 27 P61/FTOA/CIN1/ KIN1 28 P62/FTIA/CIN2/ KIN2/TMIY 29 P63/FTIB/CIN3/ KIN3 30 PA3/CIN11/ KIN11/PS2AD 31 PA2/CIN10/ KIN10/PS2AC 32 P64/FTIC/CIN4/ KIN4 33 P65/FTID/CIN5/ KIN5 34 P66/FTOB/CIN6/ KIN6/IRQ6 35 P67/CIN7/KIN7/ ...
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Section 1 Overview Pin No. Expanded Modes FP-100B TFP-100B Mode 1 46 AVSS 47 PA1/CIN9/KIN9 48 PA0/CIN8/KIN8 49 P40/TMCI0/ TxD2/IrTxD 50 P41/TMO0/ RxD2/IrRxD 51 P42/TMRI0/ SCK2/SDA1 52 P43/TMCI1 53 P44/TMO1 54 P45/TMRI1 55 P46/PWX0 56 P47/PWX1 57 PB7/D7 58 PB6/D6 ...
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Pin No. Expanded Modes FP-100B TFP-100B Mode PB3/D3 81 PB2/ D10 85 D11 86 D12 87 D13 ...
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Section 1 Overview Table 1.2 (c) H8S/2144 Group Pin Functions in Each Operating Mode Pin No. Expanded Modes FP-100B TFP-100B Mode 1 RES 1 2 XTAL 3 EXTAL 4 VCC1 5 MD1 6 MD0 7 NMI STBY 8 9 VCC2 ...
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Pin No. Expanded Modes FP-100B TFP-100B Mode 1 LWR/P90/IRQ2/ 25 ADTRG 26 P60/FTCI/CIN0/ KIN0 27 P61/FTOA/ CIN1/KIN1 28 P62/FTIA/CIN2/ KIN2/TMIY 29 P63/FTIB/CIN3/ KIN3 30 PA3/CIN11/ KIN11 31 PA2/CIN10/ KIN10 32 P64/FTIC/CIN4/ KIN4 33 P65/FTID/CIN5/ KIN5 34 P66/FTOB/CIN6/ KIN6/IRQ6 35 P67/CIN7/KIN7/ ...
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Section 1 Overview Pin No. Expanded Modes FP-100B TFP-100B Mode 1 46 AVSS 47 PA1/CIN9/KIN9 48 PA0/CIN8/KIN8 49 P40/TMCI0/ TxD2/IrTxD 50 P41/TMO0/ RxD2/IrRxD 51 P42/TMRI0/ SCK2 52 P43/TMCI1 53 P44/TMO1 54 P45/TMRI1 55 P46/PWX0 56 P47/PWX1 57 PB7/D7 58 PB6/D6 ...
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Pin No. Expanded Modes FP-100B TFP-100B Mode PB3/D3 81 PB2/ D10 85 D11 86 D12 87 D13 ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 summarizes the pin functions of this LSI. Table 1.3 Pin Functions Pin No. FP-100B Type Symbol TFP-100B Power VCC1 4 [H8S/2144 supply Group only VCC2 9 * VCL VCCB ...
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Pin No. FP-100B Type Symbol TFP-100B Operating MD1 5 mode MD0 6 control RES System 1 control RESO 100 STBY 8 Address A23 to 10, 11, 20, bus A16 21, 30, 31, 47, 48 A15 67, A0 ...
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Section 1 Overview Pin No. FP-100B Type Symbol TFP-100B WAIT Bus control HWR 19 LWR 25 AS/IOS 18 Interrupt NMI 7 signals IRQ0 25, IRQ7 97 to 99, 34, 35 16-bit free- FTCI 26 ...
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Pin No. FP-100B Type Symbol TFP-100B 8-bit timer TMO0 50 (TMR0, TMO1 53 TMR1, TMOX 35 TMRX, TMCI0 49 TMRY) TMCI1 52 TMRI0 51 TMRI1 54 TMIX 26 TMIY 28 PWM timer PW15 67, (PWM) PW0 72 ...
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Section 1 Overview Pin No. FP-100B Type Symbol TFP-100B Host HDB7 interface HDB0 (HIF) CS1, 18, 94, 25 CS2, 81, 80 ECS2 CS3, CS4 IOR 22 IOW 19 HA0 93 GA20 94 HIRQ11 52 HIRQ1 53 ...
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Pin No. FP-100B Type Symbol TFP-100B D/A DA0 44 converter DA1 45 (DAC) A/D AVCC 37 converter D/A converter AVref 36 AVSS 46 Timer VSYNCI, 28 connection HSYNCI, 52 CSYNCI, 54 VFBACKI, 29 HFBACKI 26 VSYNCO, 27 HSYNCO, 53 CLAMPO, ...
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Section 1 Overview Pin No. FP-100B Type Symbol TFP-100B I/O ports P17 P10 P27 P20 P37 P30 P47 P40 P52 ...
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Pin No. FP-100B Type Symbol TFP-100B I/O ports PA7 to 10, 11, 20, PA0 21, 30, 31, 47, 48 PB7 to 57, 58, 68, PB0 69, 80, 81, 90, 91 Note F-ZTAT and mask ROM versions of HD64F2148A, ...
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Section 1 Overview Rev. 4.00 Sep 27, 2006 page 34 of 1130 REJ09B0327-0400 ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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Section 2 CPU High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 8/16/32-bit register-register add/subtract 8-bit register-register multiply: 16 ÷ 8-bit register-register divide: 16 16-bit register-register multiply: 32 ÷ 16-bit register-register divide: ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. More general registers and control registers Eight 16-bit extended registers, and one 8-bit control register, have been added. Expanded address space Normal ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space ...
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Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in ...
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Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored ...
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Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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Section 2 CPU SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than ...
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Section 2 CPU 2.4.4 Initial Register Values Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. ...
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Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
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Section 2 CPU Data Type General Register Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * 1 , PUSH * ...
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Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Function Instruction Data MOV BWL BWL BWL BWL BWL BWL transfer ...
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Section 2 CPU Function Instruction System TRAPA — control RTE — SLEEP — LDC B STC — ANDC, ORC, B XORC NOP — Block data transfer — Legend: B: Byte W: Word L: Longword Notes: 1. Cannot be used in ...
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Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination General register (source General register * ...
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Section 2 CPU Table 2.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM * 3 STM * 3 Rev. 4.00 Sep 27, 2006 page 56 of 1130 REJ09B0327-0400 Size * 1 Function B/W/L (EAs) ...
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Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Size * 1 Function B/W/L Rd ± Rs Rd, Rd ± #IMM Performs addition or subtraction on data in two general registers, or ...
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Section 2 CPU Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS Rev. 4.00 Sep 27, 2006 page 58 of 1130 REJ09B0327-0400 Size * 1 Function B/W Rd ÷ Performs signed division on data in two general ...
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Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size * 1 Function B/W Rd, Rd Performs a logical AND operation on a general register and another general register ...
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Section 2 CPU Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR Rev. 4.00 Sep 27, 2006 page 60 of 1130 REJ09B0327-0400 Size * 1 Function B 1 (<bit-No.> of <EAd>) Sets a specified bit in ...
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Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Size * 1 Function B C (<bit-No.> of <EAd>) Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in ...
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Section 2 CPU Type Instruction Branch Bcc instructions JMP BSR JSR RTS Rev. 4.00 Sep 27, 2006 page 62 of 1130 REJ09B0327-0400 Size * 1 Function — Branches to a specified address if a specified condition is true. The branching ...
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Type Instruction System TRAPA control RTE instructions SLEEP LDC STC ANDC ORC XORC NOP Size * 1 Function — Starts trap-instruction exception handling. — Returns from an exception-handling routine. — Causes a transition to a power-down state. B/W (EAs) CCR, ...
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Section 2 CPU Type Instruction Block data EEPMOV.B transfer instructions EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS ...
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Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op cc Figure 2.12 Instruction Formats (Examples) 2.6.5 Notes on ...
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Section 2 CPU absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 Addressing Modes No. Addressing Mode 1 ...
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed ...
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Section 2 CPU Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit- manipulation instructions contain 3-bit immediate ...
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Specified Branch address by @aa:8 (a) Normal Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access branch address, the least significant bit is regarded ...
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Section 2 CPU Table 2.6 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct (Rn Register indirect (@ERn Register indirect with displacement @(d:16, ERn) or @(d:32, ERn disp ...
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Addressing Mode and No. Instruction Format 5 Absolute address @aa:8 op abs @aa:16 op abs @aa:24 op abs @aa:32 op abs 6 Immediate #xx:8/#xx:16/#xx:32 op IMM 7 Program-counter relative @(d:8, PC)/@(d:16, PC) op disp Effective Address Calculation 31 Don’t care ...
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Section 2 CPU Addressing Mode and No. Instruction Format 8 Memory indirect @@aa:8 Normal mode op abs Advanced mode op abs Rev. 4.00 Sep 27, 2006 page 72 of 1130 REJ09B0327-0400 Effective Address Calculation H'000000 abs ...
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Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. ...
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Section 2 CPU End of bus request Bus-released state End of exception handling Exception-handling state RES = high Reset state * 1 From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. ...
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Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table ...
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Section 2 CPU Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU ...
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Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, hardware ...
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Section 2 CPU 2.9 Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred “state.” The memory cycle ...
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Bus cycle Address bus Unchanged AS High RD High HWR, LWR High Data bus High impedance Figure 2.18 Pin States during On-Chip Memory Access T1 Rev. 4.00 Sep 27, 2006 page 79 of 1130 Section 2 CPU REJ09B0327-0400 ...
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Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 ...
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Address bus AS RD HWR, LWR Data bus Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state ...
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Section 2 CPU 2.10 Usage Note 2.10.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. If ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection This LSI has three operating modes (modes 1 to 3). These modes enable selection of the CPU operating mode and enabling/disabling of on-chip ROM, by setting the mode pins ...
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Section 3 MCU Operating Modes 3.1.2 Register Configuration This LSI have a mode control register (MDCR) that indicates the inputs at the mode pins (MD1 and MD0), a system control register (SYSCR) and bus control register (BCR) that control the ...
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Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, this bit is fixed at 1 and cannot be modified. In modes 2 and 3, this bit has an initial value of 0, and can be read and written. ...
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Section 3 MCU Operating Modes Bit 6—IOS Enable (IOSE): Controls the function of the AS/IOS pin in expanded mode. Bit 6 IOSE Description The AS/IOS pin functions as the address strobe pin (AS) 0 (Low output when accessing an external ...
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Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip ...
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Section 3 MCU Operating Modes 3.2.4 Serial Timer Control Register (STCR) Bit 7 IICS IICX1 Initial value 0 Read/Write R/W R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option ...
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Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), the power-down mode control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and the supporting module control register (PCSR and SYSCR2). ...
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Section 3 MCU Operating Modes 3.3.3 Mode 3 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set ...
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Memory Map in Each Operating Mode Figures 3.1 to 3.5 show memory maps for each of the operating modes. The address space is 64 kbytes in modes 1 and 3 (normal modes), and 16 Mbytes in mode 2 (advanced ...
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Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E080 On-chip RAM* H'EFFF External address space H'FE50 Internal I/O registers 2 H'FEFF H'FF00 On-chip RAM (128 bytes) * H'FF7F H'FF80 Internal ...
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Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 H'01FFFF H'020000 External address H'FFE080 On-chip RAM * H'FFEFFF External address H'FFFE50 Internal I/O registers 2 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF Note: * External ...
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Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E080 On-chip RAM * H'EFFF External address space H'F800 Reserved area H'FE4F H'FE50 Internal I/O registers 2 H'FEFF H'FF00 On-chip RAM (128 ...
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Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'01FFFF H'020000 External address H'FFE080 On-chip RAM * H'FFEFFF External address H'FFF800 Reserved area H'FFFE4F H'FFFE50 Internal I/O registers 2 H'FFFEFF H'FFFF00 On-chip RAM (128 bytes) ...
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Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E080 On-chip RAM * H'EFFF External address space H'FE50 Internal I/O registers 2 H'FEFF H'FF00 On-chip RAM (128 bytes) * H'FF7F H'FF80 ...
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Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'017FFF Reserved area H'01FFFF H'020000 External address space H'FFE080 On-chip RAM * H'FFEFFF External address space H'FFFE50 Internal I/O registers 2 H'FFFEFF H'FFFF00 On-chip RAM (128 ...
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Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E080 Reserved area * H'E880 On-chip RAM * H'EFFF External address space H'FE50 Internal I/O registers 2 H'FEFF H'FF00 On-chip RAM (128 ...
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Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'00FFFF Reserved area H'01FFFF H'020000 External address H'FFE080 Reserved area * H'FFE880 On-chip RAM * H'FFEFFF External address H'FFFE50 Internal I/O registers 2 H'FFFEFF H'FFFF00 H'FFFF7F ...
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Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E080 Reserved area * H'E880 On-chip RAM * H'EFFF External address space H'F800 Reserved area H'FE4F H'FE50 Internal I/O registers 2 H'FEFF ...
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Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'00FFFF Reserved area H'01FFFF H'020000 External address H'FFE080 Reserved area * H'FFE880 On-chip RAM * H'FFEFFF External address H'FFF800 H'FFFE4F H'FFFE50 Internal I/O registers 2 H'FFFEFF ...
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Section 3 MCU Operating Modes Rev. 4.00 Sep 27, 2006 page 102 of 1130 REJ09B0327-0400 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack. 2. The interrupt mask bits ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use Direct transition External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Internal interrupt * 2 Notes: ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the MCU enters the reset state. A reset initializes the internal state of the CPU ...
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RES Internal address bus Internal read signal Internal write signal Internal data bus (1) Reset exception vector address ((1) = H'0000) (2) Start address (contents of reset exception vector address) (3) Start address ((3) = (2)) (4) First program instruction ...
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Section 4 Exception Handling RES Address bus RD HWR, LWR D15 to D8 (1) (3) Reset exception vector address ((1) = H'0000, (3) = H'0001) (2) (4) Start address (contents of reset exception vector address) (5) Start address ((5) = ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI and IRQ7 to IRQ0) from 23 input pins (NMI, IRQ7 to IRQ0, and KIN15 to KIN0), and internal sources in the on-chip supporting modules. Figure 4.4 shows ...
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Section 4 Exception Handling 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address ...
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Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP Note: * Ignored on return. Figure 4.5 (1) Stack Status after Exception Handling (Normal Mode) Figure 4.5 ...
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Section 4 Exception Handling 4.6 Notes on Use of the Stack When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features This LSI control interrupts by means of an interrupt controller. The interrupt controller has the following features: Two interrupt control modes Either of two interrupt control modes can be set by means ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt requests SWDTEND to PS2IC ...
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Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests KIN15 to KIN0 Input Key input interrupt requests ...
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Section 5 Interrupt Controller 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status ...
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Register Descriptions 5.2.1 System Control Register (SYSCR) Bit 7 6 CS2E IOSE Initial value 0 0 Read/Write R/W R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI, among other ...
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Section 5 Interrupt Controller 5.2.2 Interrupt Control Registers (ICRA to ICRC) Bit 7 ICR7 ICR6 Initial value 0 Read/Write R/W R/W The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts ...
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IRQ Enable Register (IER) Bit 7 IRQ7E IRQ6E Initial value 0 Read/Write R/W R/W IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H' reset ...
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Section 5 Interrupt Controller ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. Each of the ISCR registers is initialized to ...
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Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF Description 0 [Clearing conditions] Cleared by reading IRQnF when set to 1, then writing 0 in ...
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Section 5 Interrupt Controller 5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) 7 Bit KMIMR7 KMIMR6 Initial value 1 Read/Write R/W R/W KMIMR is an 8-bit readable/writable register that performs mask control for the keyboard matrix interrupt inputs (pins KIN7 to ...
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Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR15 to KMIMR8): These bits control key-sense input interrupt requests (KIN15 to KIN8). Bits KMIMR15 to KMIMR8 Description 0 Key-sense input interrupt requests enabled 1 Key-sense input interrupt requests disabled ...
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Section 5 Interrupt Controller If any of bits KMIMR15 to KMIMR8 is cleared to 0, interrupt input from the IRQ7 pin will be ignored. When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins, ...
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Break Address Registers (BARA, BARB, BARC) Bit 7 BARA A23 A22 Initial value 0 Read/Write R/W R/W Bit 7 BARB A15 A14 Initial value 0 Read/Write R/W R/W Bit 7 A7 BARC Initial value 0 Read/Write ...
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Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts. 5.3.1 External Interrupts There are nine external interrupt sources from 25 input pins (23 actual pins): NMI, IRQ7 to IRQ0, ...
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IRQnSCA, IRQnSCB Edge/level detection circuit IRQn input Note Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.4 shows the timing of IRQnF setting. IRQn input pin IRQnF Figure 5.4 Timing of IRQnF Setting The ...
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Section 5 Interrupt Controller Interrupts KIN15 to KIN0 Interrupts KIN15 to KIN0 are requested by input signals at pins KIN15 to KIN 0. When any of pins KIN15 to KIN0 are used as key-sense inputs, the corresponding KMIMR bits should ...
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Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8 SWDTEND (software activation interrupt end) WOVI0 (interval timer) WOVI1 (interval timer) Address break (PC ...
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Section 5 Interrupt Controller Interrupt Source CMIA0 (compare-match A) CMIB0 (compare-match B) OVI0 (overflow) Reserved CMIA1 (compare-match A) CMIB1 (compare-match B) OVI1 (overflow) Reserved CMIAY (compare-match A) CMIBY (compare-match B) OVIY (overflow) ICIX (input capture X) IBF1 (IDR1 reception completed) ...
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Interrupt Source IICI1 (1-byte transmission/ reception completed) Reserved PS2IA (reception completed A) PS2IB (reception completed B) PS2IC (reception completed C) Reserved Reserved Vector Address Origin of Interrupt Vector Normal Source Number Mode IIC channel 1 94 H'00BC (option) 95 H'00BE ...
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Section 5 Interrupt Controller 5.4 Address Breaks 5.4.1 Features With this LSI possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an ...
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Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the ...
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Section 5 Interrupt Controller • Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction fetch fetch Address bus H'0310 H'0312 NOP execution Break request signal H'0310 NOP H'0312 NOP H'0314 NOP H'0316 NOP • Program ...
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Interrupt Operation 5.5.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in this LSI differ depending on the interrupt control mode. NMI and address break interrupts are accepted at all times except in the reset state and the hardware ...
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Section 5 Interrupt Controller Figure 5.7 shows a block diagram of the priority decision circuit. acceptance control Interrupt source Interrupt control modes Figure 5.7 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control and 3-Level Control In interrupt control modes ...
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Table 5.6 Interrupts Selected in Each Interrupt Control Mode Interrupt Control Mode 0 1 Legend: *: Don’t care Default Priority Determination The priority is determined for the selected interrupt, and a vector number is generated. If the same value is ...
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Section 5 Interrupt Controller 5.5.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the ...
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Program execution state Interrupt generated? Yes Control level 1 interrupt? Yes No IRQ0? No Yes IRQ1? Yes PS2IC? Yes Save PC and CCR Read vector address Branch to interrupt handling routine Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance ...
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Section 5 Interrupt Controller 5.5.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU’s CCR, and ICR. Control level 0 interrupt requests ...
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Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. 2. When ...
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Section 5 Interrupt Controller Control level 1 interrupt? No IRQ0? Yes IRQ1 Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Rev. 4.00 Sep 27, 2006 page 142 of 1130 REJ09B0327-0400 Program execution state Interrupt generated? ...
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Interrupt Exception Handling Sequence Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Section 5 Interrupt Controller Figure 5.11 Interrupt Exception Handling Rev. 4.00 Sep 27, 2006 page 144 of 1130 REJ09B0327-0400 ...
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Interrupt Response Times This LSI are capable of fast word access to on-chip memory, and high-speed processing can be achieved by providing the program area in on-chip ROM and the stack area in on-chip RAM. Table 5.8 shows interrupt ...
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Section 5 Interrupt Controller 5.6 Usage Notes 5.6.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an ...
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The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.6.2 Instructions That Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any ...
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Section 5 Interrupt Controller 5.7 DTC Activation by Interrupt 5.7.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available: Interrupt request to CPU Activation request to DTC Both of the above For ...
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Operation The interrupt controller has three main functions in DTC control. Selection of Interrupt Source possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC. After ...
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Section 5 Interrupt Controller Usage Note SCI, IIC, and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent upon the DISEL bit. Rev. 4.00 Sep 27, 2006 page 150 ...
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Section 6 Bus Controller 6.1 Overview This LSI have a built-in bus controller (BSC) that allows external address space bus specifications, such as bus width and number of access states set. The bus controller also has a bus ...
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Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. External bus control signals WAIT Figure 6.1 Block Diagram of Bus Controller Rev. 4.00 Sep 27, 2006 page 152 of 1130 REJ09B0327-0400 Bus ...
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Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol AS Address strobe IOS I/O select RD Read HWR High write LWR Low write WAIT Wait 6.1.4 Register Configuration Table 6.2 ...
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Section 6 Bus Controller 6.2 Register Descriptions 6.2.1 Bus Control Register (BCR) Bit 7 ICIS1 ICIS0 Initial value 1 Read/Write R/W R/W BCR is an 8-bit readable/writable register that specifies the external memory space access mode, and the extent of ...