DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 216

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 Instruction Descriptions
2.2.57 (3)
SHAL (SHift Arithmetic Left)
Operation
Rd (left arithmetic shift)
Assembly-Language Format
SHAL.W Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The
most significant bit (bit 15) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Rev. 4.00 Feb 24, 2006 page 200 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHAL (W)
Mnemonic
SHAL.W
C
Rd
MSB
b15
Operands
Rd
. . . . . .
1st byte
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 15.
2nd byte
9
Instruction Format
cleared to 0.
cleared to 0.
cleared to 0.
—
I
rd
UI H
—
—
3rd byte
LSB
b0
—
U
N
0
4th byte
Shift Arithmetic
Z
V
States
No. of
C
1