DF2158VBP25 Renesas Electronics America, DF2158VBP25 Datasheet
DF2158VBP25
Specifications of DF2158VBP25
HD64F2158VBP25
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DF2158VBP25 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2158 Group, 16 H8S/2158 F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions in This Edition The list of revisions is a summary of points that ...
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The H8S/2158 is a microcomputer made up of the H8S/2000 CPU employing Renesas Technology’s original architecture as its core, and the peripheral functions required to configure a system, such as a notebook PC and portable information appliance products. The H8S/2000 ...
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URL: http://www.keitaide-music.org/ 3. F-ZTAT™ trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2158 in the design of application ...
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H8S/2158 manuals: Document Title H8S/2158 Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual User’s manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual H8S, H8/300 Series Simulator/Debugger User’s Manual H8S, H8/300 Series ...
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Rev. 3.00 Jan 25, 2006 page viii of lii ...
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Main Revisions in This Edition Item Page All — 5.3.4 IRQ Sense 79 Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) 6.3.1 Bus Control 107 Register (BCR) 8.2.15 Data Transfer 179 ID Read/Write Select Register B (DTIDSRB) 9.9.2 Port 9 Data 251 ...
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Item Page 13.3.4 Time Control 322 Register (TCR) Table 13.2 Clock Input to TCNT and Count Condition — — 13.7 Input Capture 336 Operation 13.9.6 Mode Setting 344 with Cascaded Connection 15.3 Register 378 Descriptions 16.3.7 Serial Status 402 Register ...
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Item Page 16.3.9 Bit Rate 405 Register (BRR) Table 16.2 Relationship between N Setting in BRR and Bit Rate B 16.3.10 Serial 412 Interface Control Register (SCICR) 16.7.8 Clock Output 455 Control 16.8 IrDA Operation 456 Figure 16.36 IrDA Block ...
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Item Page 17.3.8 IIC Operation 498 Reservation Adapter Status Register A (ICSRA) 17.3.10 IIC 506 Operation Reservation Adapter Status Register C (ICSRC) Figure 17.3 State 507 Transitions of TDRE, SDRF, and RDRF Bits 17.5.3 Master 520 Receive Operation 17.7 Usage ...
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Item Page 17.7 Usage Notes 549, 550 Revision (See Manual for Details) Description added 15. Notes on WAIT function (a) Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock ...
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Item Page 17.7 Usage Notes 550, 551 Rev. 3.00 Jan 25, 2006 page xiv of lii Revision (See Manual for Details) 16. Notes on Arbitration Lost 2 The I C bus interface recognizes the data in transmit/receive frame as an ...
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Item Page 17.7 Usage Notes 551 18.3.1 USB Data 557 FIFO Table 18.2 FIFO Configuration 25.4.1 TAP 755 Controller State Transitions Figure 25.2 TAP Controller State Transitions 28.1 Register 792 Addresses (Address Order) 793 28.1 Register Bits 804 805 Revision ...
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Item Page 28.1 Register Bits 808 28.2 Register Bits 808 28.3 Register States 815 in Each Operating Mode 816 29.6 Flash Memory 859 Characteristics Table 29.18 Flash Memory Characteristics 860 863 B. Product Lineup C. Package Dimensions Figure C.1 Package ...
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Section 1 Overview ............................................................................................................. 1.1 Features ............................................................................................................................. 1.2 Internal Block Diagram..................................................................................................... 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Arrangement in Each Operating Mode .......................................................... 1.3.3 Pin Functions ....................................................................................................... Section 2 CPU ...................................................................................................................... 17 2.1 Features ............................................................................................................................. 17 2.1.1 ...
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Effective Address Calculation.............................................................................. 48 2.8 Processing States............................................................................................................... 50 2.9 Usage Notes ...................................................................................................................... 52 2.9.1 Note on TAS Instruction Usage ........................................................................... 52 2.9.2 Note on Bit Manipulation Instructions................................................................. 52 2.9.3 EEPMOV Instruction........................................................................................... 54 Section 3 MCU Operating Modes 3.1 Operating ...
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Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6) Wake-Up Event Interrupt Mask Register (WUEMR3) ........................................ 83 5.4 Interrupt Sources ............................................................................................................... 84 5.4.1 External Interrupts ............................................................................................... 84 5.4.2 Internal Interrupts................................................................................................. 86 5.5 Interrupt Exception Handling Vector Table...................................................................... 86 5.6 Interrupt Control ...
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Basic Operation Timing ....................................................................................... 138 6.7.4 Wait Control ........................................................................................................ 140 6.8 Idle Cycle .......................................................................................................................... 141 6.9 Bus Arbitration.................................................................................................................. 142 6.9.1 Bus Master Priority .............................................................................................. 142 6.9.2 Bus Transfer Timing ............................................................................................ 143 Section 7 Data Transfer Controller (DTC) 7.1 Features ...
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Section 8 RAM-FIFO Unit (RFU) 8.1 Features ............................................................................................................................. 167 8.2 Register Descriptions ........................................................................................................ 169 8.2.1 FIFO Status/Register/Pointer (FSTR) .................................................................. 169 8.2.2 Base Address Register (BAR).............................................................................. 170 8.2.3 Read Address Pointer (RAR) ............................................................................... 170 8.2.4 Write Address Pointer (WAR) ............................................................................. 171 ...
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Section 9 I/O Ports .............................................................................................................. 205 9.1 Port 1................................................................................................................................. 209 9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 209 9.1.2 Port 1 Data Register (P1DR)................................................................................ 210 9.1.3 Port 1 Pull-Up MOS Control Register (P1PCR).................................................. 210 9.1.4 Pin Functions ....................................................................................................... 211 9.1.5 ...
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Port 9 Data Direction Register (P9DDR)............................................................. 250 9.9.2 Port 9 Data Register (P9DR)................................................................................ 251 9.9.3 Pin Functions ....................................................................................................... 251 9.10 Port A................................................................................................................................ 254 9.10.1 Port A Data Direction Register (PADDR) ........................................................... 254 9.10.2 Port A Output Data Register (PAODR) ...
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Output Compare Registers A and B (OCRA and OCRB).................................... 290 12.3.3 Input Capture Registers (ICRA to ICRD) ................................................ 290 12.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) ......................... 291 12.3.5 Output Compare Register DM ...
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Operation........................................................................................................................... 330 13.4.1 Pulse Output......................................................................................................... 330 13.5 Operation Timing.............................................................................................................. 331 13.5.1 TCNT Count Timing............................................................................................ 331 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 332 13.5.3 Timing of Timer Output at Compare-Match........................................................ 332 13.5.4 Timing of Counter Clear ...
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Section 15 Watchdog Timer (WDT) 15.1 Features ............................................................................................................................. 373 15.2 Input/Output Pins .............................................................................................................. 375 15.3 Register Descriptions ........................................................................................................ 375 15.3.1 Timer Counter (TCNT)........................................................................................ 375 15.3.2 Timer Control/Status Register (TCSR) ................................................................ 376 15.4 Operation........................................................................................................................... 379 15.4.1 Watchdog Timer Mode ........................................................................................ 379 ...
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SCI Initialization (Asynchronous Mode) ............................................................. 424 16.4.6 Serial Data Transmission (Asynchronous Mode) ................................................ 425 16.4.7 Serial Data Reception (Asynchronous Mode)...................................................... 427 16.5 Multiprocessor Communication Function......................................................................... 431 16.5.1 Multiprocessor Serial Data Transmission ............................................................ 432 16.5.2 Multiprocessor Serial Data Reception ................................................................. ...
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Note on CRC Operation Circuit........................................................................... 472 2 Section Bus Interface (IIC) 17.1 Features ............................................................................................................................. 473 17.2 Input/Output Pins .............................................................................................................. 476 17.3 Register Descriptions ........................................................................................................ 476 2 17.3 Bus Data Register (ICDR) ............................................................................. 477 17.3.2 ...
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USB Data FIFO.................................................................................................... 557 18.3.2 Endpoint Size Register 1 (EPSZR1) .................................................................... 558 18.3.3 Endpoint Data Registers 0S, 0O, 0I and 3 (EPDR0S, EPDR0O, EPDR0I, EPDR1, EPDR2, and EPDR3)........................... 559 18.3.4 Endpoint Valid Size Registers 0S, 0O, 0I, ...
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Command Type Register (CMDTYR)................................................................. 632 19.3.3 Response Type Register (RSPTYR) .................................................................... 633 19.3.4 Transfer Byte Number Count Register (TBCR) .................................................. 636 19.3.5 Transfer Block Number Counter (TBNCR)......................................................... 636 19.3.6 Command Registers (CMDR0 to CMDR5) ............................................... 637 ...
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Usage Notes ...................................................................................................................... 695 Section 22 A/D Converter 22.1 Features ............................................................................................................................. 697 22.2 Input/Output Pins .............................................................................................................. 699 22.3 Register Descriptions ........................................................................................................ 700 22.3.1 A/D Data Registers (ADDRA to ADDRD).............................................. 700 22.3.2 A/D Control/Status Register (ADCSR) ............................................................... ...
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Program/Program-Verify ..................................................................................... 733 24.8.2 Erase/Erase-Verify............................................................................................... 735 24.9 Program/Erase Protection.................................................................................................. 737 24.9.1 Hardware Protection ............................................................................................ 737 24.9.2 Software Protection.............................................................................................. 737 24.9.3 Error Protection.................................................................................................... 737 24.10 Interrupts during Flash Memory Programming/Erasing ................................................... 738 24.11 Programmer Mode ............................................................................................................ 738 24.12 Usage Notes ...
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Section 27 Power-Down Modes 27.1 Register Descriptions ........................................................................................................ 772 27.1.1 Standby Control Register (SBYCR) .................................................................... 772 27.1.2 Low-Power Control Register (LPWRCR) ........................................................... 774 27.1.3 System Control Register 2 (SYSCR2) ................................................................. 775 27.1.4 Module Stop Control Registers H and L (MSTPCRH, ...
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B. Product Lineup.................................................................................................................. 863 C. Package Dimensions ......................................................................................................... 864 Index .......................................................................................................................................... 865 Rev. 3.00 Jan 25, 2006 page xxxiv of lii ...
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Section 1 Overview Figure 1.1 Internal Block Diagram ........................................................................................ Figure 1.2 Pin Arrangement (TBP-112A: Top View)............................................................ Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) .............................................................. 21 Figure 2.2 Stack Structure in Normal Mode .......................................................................... 21 Figure 2.3 Exception ...
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Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1.................................................................................................................. 96 Figure 5.8 Interrupt Exception Handling ............................................................................... 97 Figure 5.9 Interrupt Control for DTC..................................................................................... 99 Figure 5.10 Conflict between Interrupt Generation and Disabling .......................................... 101 Section ...
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Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ............................................................................................ 162 Figure 7.11 DTC Operation Timing (Example of Chain Transfer).......................................... 162 Section 8 RAM-FIFO Unit (RFU) Figure 8.1 Block Diagram of RFU......................................................................................... 168 Figure ...
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Figure 12.9 Buffered Input Capture Timing ............................................................................ 303 Figure 12.10 Buffered Input Capture Timing (BUFEA = 1)...................................................... 304 Figure 12.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ................. 304 Figure 12.12 Timing of Output Compare Flag ...
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Figure 14.6 2fH Modification Timing Chart............................................................................ 364 Figure 14.7 Fall Modification and IHI Synchronization Timing Chart.................................... 366 Figure 14.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart............................................... 369 Figure 14.9 CBLANK Output Waveform Generation ............................................................. 372 Section 15 Watchdog Timer (WDT) Figure ...
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Figure 16.18 Sample SCI Initialization Flowchart..................................................................... 438 Figure 16.19 Sample SCI Transmission Operation in Clocked Synchronous Mode.................. 439 Figure 16.20 Sample Serial Transmission Flowchart................................................................. 440 Figure 16.21 Example of SCI Receive Operation in Clocked Synchronous Mode.................... 441 Figure 16.22 Sample ...
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Figure 17 Bus Formats (Serial Formats)......................................................................... 516 2 Figure 17 Bus Timing ..................................................................................................... 517 Figure 17.7 Master Transmit Mode Operation Timing Example (MLS = WAIT = 0) ............ 519 Figure 17.8 Master Receive Mode Operation ...
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Figure 18.9 Operation on Receiving an OUT Token (EP5-OUT: Initial FIFO Is Full) ........... 613 Figure 18.10 Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Full) ................... 614 Figure 18.11 Operation on Receiving an IN Token (EP2-IN: Initial ...
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Figure 21.2 D/A Converter Operation Example ...................................................................... 694 Section 22 A/D Converter Figure 22.1 Block Diagram of A/D Converter......................................................................... 698 Figure 22.2 A/D Conversion Timing ....................................................................................... 707 Figure 22.3 External Trigger Input Timing.............................................................................. 708 Figure 22.4 A/D Conversion Accuracy Definitions ...
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Figure 26.9 Processing for X1 and X2 Pins ............................................................................. 769 Section 27 Power-Down Modes Figure 27.1 Mode Transition Diagram..................................................................................... 779 Figure 27.2 Medium-Speed Mode Timing............................................................................... 782 Figure 27.3 Software Standby Mode Application Example..................................................... 784 Figure 27.4 Hardware Standby Mode Timing.......................................................................... ...
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Appendix Figure C.1 Package Dimensions (TBP-112A) ......................................................................... 864 Rev. 3.00 Jan 25, 2006 page xlv of lii ...
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Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ Table 1.2 Pin Functions.......................................................................................................... Section 2 CPU Table 2.1 Instruction Classification........................................................................................ 33 Table 2.2 Operation Notation ................................................................................................. 34 Table 2.3 Data Transfer Instructions ...................................................................................... 35 Table 2.4 Arithmetic ...
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Table 5.7 Interrupt Response Times....................................................................................... 98 Table 5.8 Number of States in Interrupt Handling Routine Execution Status........................ 98 Table 5.9 Interrupt Source Selection and Clearing Control.................................................... 100 Section 6 Bus Controller Table 6.1 Pin Configuration ................................................................................................... 105 Table 6.2 Address ...
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Table 9.4 Port 3 Input Pull-Up MOS States ........................................................................... 222 Table 9.5 Port 6 Input Pull-Up MOS States ........................................................................... 244 Table 9.6 Port A Input Pull-Up MOS States .......................................................................... 257 Section 10 8-Bit PWM Timer (PWM) Table 10.1 Pin Configuration ...
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Table 14.9 Examples of TCR, TCSR, TCORA, TCORB, OCRAR, OCRAF, and TOCR Settings................................................................................................. 368 Table 14.10 HSYNCO Output Modes........................................................................................ 370 Table 14.11 VSYNCO Output Modes........................................................................................ 371 Section 15 Watchdog Timer (WDT) Table 15.1 Pin Configuration ................................................................................................... 375 Table 15.2 WDT ...
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Section 18 Universal Serial Bus Interface (USB) Table 18.1 Pin Configuration ................................................................................................... 555 Table 18.2 FIFO Configuration................................................................................................ 557 Table 18.3 Port 6 Functions ..................................................................................................... 595 Table 18.4 USB Function Core and Slave CPU Functions ...................................................... 603 Table 18.5 Packets Included ...
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Section 25 User Debug Interface (H-UDI) Table 25.1 Pin Configuration ................................................................................................... 743 Table 25.2 H-UDI Register Serial Transfer.............................................................................. 744 Table 25.3 Correspondence between Pins and Boundary Scan Register.................................. 747 Section 26 Clock Pulse Generator Table 26.1 Damping Resistance Values ................................................................................... ...
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Rev. 3.00 Jan 25, 2006 page lii of lii ...
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Features High-speed H8S/2000 CPU with an internal 16-bit architecture Upward-compatible with H8/300 CPU and H8/300H CPU on an object level Sixteen 16-bit general registers 65 basic instructions Various peripheral functions Data transfer controller (DTC) RAM-FIFO unit (RFU) 8-bit PWM ...
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Section 1 Overview Compact package Package Code TFBGA-112 TBP-112A 1.2 Internal Block Diagram XTAL EXTAL X1 X2 MD2 MD1 MD0 RES RESO STBY FWE NMI ETRST ETMS ETDO ETDI ETCK USDP USDM LWR/P90 CPCS2/P91 CPCS1/P92 CPOE/RD/P93 CPWE/HWR/P94 IOS/AS/P95 EXCL/ /P96 ...
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Pin Description 1.3.1 Pin Arrangement Pin Pin Name No. A1 (Reserved) A2 FWE A3 P83/ExIRQ11/SDA1 A4 P80/ExIRQ8/SCL0 A5 P84/ExIRQ12/SCK0/ExTMI0 A6 P36/D14/CPD14/WUE14 A7 P33/D11/CPD11/WUE11/MCDATDIR/MCCSA A8 P30/D8/CPD8/WUE8/MCCLK A9 P87/ExIRQ15/ADTRG/ExTMIY/USEXCL A10 P12/A2/PW2/CPA2 A11 (Reserved) B1 XTAL RES B2 B3 P53/IRQ11/RxD1/IrRxD B4 P82/ExIRQ10/SCL1 ...
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Section 1 Overview 1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin No. Extended Mode Modes 2 and 3 TBP-112A (EXPE = 1) RES B2 B1 XTAL C2 EXTAL MD2 C1 D3 MD1 ...
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Pin No. Extended Mode Modes 2 and 3 TBP-112A (EXPE = 1) L2 P61/FTOA/CIN1/ KIN1/VSYNCO * H4 P62/FTIA/CIN2/ KIN2/VSYNCI * 1 K3 P63/FTIB/CIN3/ KIN3/VFBACKI * L3 ETDI J4 ETCK K4 P64/FTIC/CINk4/ KIN4/CLAMPO * L4 P65/FTID/CIN5/ KIN5/CSYNCI * 1 H5 P66/FTOB/CIN6/ ...
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Section 1 Overview Pin No. Extended Mode Modes 2 and 3 TBP-112A (EXPE = 1) K10 P40/IRQ0/TMI0/ExMCCLK K11 P41/IRQ1/TMI1/ExMCCMD/ ExMCTxD/HSYNCI H8 P42/IRQ2/TMO0/ExMCDAT/ ExMCRxD J10 P43/IRQ3/TMO1/ ExMCDATDIR/ExMCCSA/ HSYNCO J11 P44/IRQ4/TMIX/ ExMCCMDDIR/ExMCCSB H9 P45/IRQ5/TMIY H10 P46/IRQ6/TMOX H11 P47/IRQ7/TMOY G8, G9 VCC G11 ...
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Pin No. Extended Mode Modes 2 and 3 TBP-112A (EXPE = 1) A10 P12/A2/CPA2 D8 P11/A1/CPA1 B9 P10/A0/CPA0 A9 P87/ExIRQ15/ADTRG/ExTMIY/ USEXCL C8 P86/ExIRQ14/SCK2/ExTMIX A8 D8/CPD8 D7 D9/CPD9 C7 D10/CPD10 A7 D11/CPD11 B7 D12/CPD12 C6 D13/CPD13 A6 D14/CPD14 B6 D15/CPD15 D6 ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Type Symbol Power VCC supply VCL VSS Clock XTAL EXTAL EXCL X1 X2 MD2 Operating mode MD1 control MD0 RES System control RESO STBY FWE Rev. 3.00 Jan 25, 2006 ...
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Type Symbol Address A17 to A0 bus Data bus D15 CPREG Compact- Flash CPA10 to control CPA0 CPD15 to CPD0 CPCS2 CPCS1 CPWAIT CPOE CPWE Pin No. TBP-112A I/O Name and Function J8, K9 Output ...
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Section 1 Overview Type Symbol WAIT Bus control RD HWR LWR AS/IOS CS256 Interrupts NMI IRQ15 to IRQ0 ExIRQ15 to ExIRQ2 ETRST On-chip emulator ETMS ETDO ETDI ETCK Rev. 3.00 Jan 25, 2006 page 10 of 872 REJ09B0286-0300 Pin No. ...
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Type Symbol PWM timer PW15 to PW0 (PWM) 14-bit PWX1 PWM timer PWX0 (PWMX) 16-bit free FTCI running FTOA timer (FRT) FTOB FTIA to FTID 8-bit timer TMO0 (TMR_0, TMO1 TMR_1, TMOX TMR_X, TMOY TMR_Y) TMI0 TMI1 TMIX TMIY ExTMI0 ...
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Section 1 Overview Type Symbol Serial TxD0 to TxD2 communi- cation RxD0 to RxD2 Interface (SCI_0, SCK0 to SCK2 SCI_1, SCI_2) SSE0I SSE2I SCI with IrTxD IrDA (SCI) IrRxD bus SCL0 interface SCL1 (IIC) SDA0 SDA1 KIN9 ...
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Type Symbol A/D AVCC converter D/A converter AVref AVSS Universal USDP serial bus USDM (USB) USEXCL DrVCC DrVSS SPEED SUSPEND TXENL TXDMNS TXDPLS XVERDATA DMNS DPLS Pin No. TBP-112A I/O Name and Function K5, J6 Input Analog power supply pins ...
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Section 1 Overview Type Symbol Multimedia ExMCCLK card MCCLK interface ExMCTxD (MCIF) MCTxD ExMCRxD MCRxD ExMCCSA ExMCCSB MCCSA MCCSB ExMCCMD MCCMD ExMCDAT MCDAT ExMCDATDIR ExMCCMDDIR MCDATDIR MCCMDDIR I/O ports P17 to P10 P27 to P20 P37 to P30 P47 to ...
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Type Symbol I/O ports P67 to P60 P77 to P72 P87 to P80 P97 to P90 PA1, PA0 Note: * MMC mode is MultiMediaCard mode. Pin No. TBP-112A I/O Name and Function J5, H5 Input/ Eight input/output pins L4, K4 ...
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Section 1 Overview Rev. 3.00 Jan 25, 2006 page 16 of 872 REJ09B0286-0300 ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU 16 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 16-bit register-register divide: 20 states (DIVXU.W) Two CPU operating modes Normal mode Advanced mode Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. Extended address space Normal ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's ...
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H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 H'0007 H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode (16 bits) ...
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Section 2 CPU 2.2.2 Advanced Mode Address space Linear access to a maximum address space of 16 Mbytes is possible. Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and ...
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Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...
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Bit Bit Name Initial Value 1 V Undefined 0 C Undefined 2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the ...
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Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn : General register General register General register R RnH : General register RH RnL ...
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...
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Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * 1 , PUSH * LDM, STM * ...
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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register ...
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Table 2.3 Data Transfer Instructions Size * 1 Instruction Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size * Function ADD B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Subtraction ...
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Table 2.4 Arithmetic Operations Instructions (2) Instruction Size * Function DIVXS B/W Rd Performs signed division on data in two general registers: either 16 bits 8 bits quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares ...
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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size * Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on ...
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Table 2.7 Bit Manipulation Instructions (1) Instruction Size * Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Size * Instruction Function BXOR B C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ...
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Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...
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Section 2 CPU Table 2.9 System Control Instructions Size * Instruction Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the memory ...
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Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next: EEPMOV.W — else next: Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set ...
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Section 2 CPU (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 Addressing ...
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Table 2.11 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory indirect 2.7.1 Register ...
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Section 2 CPU Register Indirect with Pre-Decrement—@-ERn: The value subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The ...
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Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated ...
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Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table ...
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Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Effective Address Calculation Operand is immediate data. PC contents Sign extension Memory contents Memory contents Rev. 3.00 Jan 25, 2006 page 49 of 872 Section 2 ...
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Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. Reset state In this state ...
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End of bus request Bus-released state End of exception handling Exception-handling state RES = high Reset state * 1 From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A ...
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Section 2 CPU 2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage The TAS instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. The TAS instruction can be used as a user-defined intrinsic function. 2.9.2 Note ...
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BCLR instruction executed BCLR #0, @P4DDR After executing BCLR P47 P46 Input/output Output Output Pin state Low High level level DDR [Description on Operation] 1. When the BCLR instruction is executed, first the CPU reads ...
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Section 2 CPU 2.9.3 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction that transfers the byte size of data indicated which starts from the address indicated by ER5, to the address indicated by ER6. ER5 ER5 + ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports two operating modes (modes 2 and 3). The operating mode is determined by the setting of the mode pins (MD2, MD1, and MD0). Table 3.1 shows the MCU ...
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Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit Bit Name Initial Value 7 EXPE 0 6 — All ...
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System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables register access to the on-chip peripheral modules, and enables or disables ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 2 NMIEG 0 1 KINWUE 0 0 RAME 1 Rev. 3.00 Jan 25, 2006 page 58 of 872 REJ09B0286-0300 R/W Description R/W NMI Edge Select Selects the valid edge of ...
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Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit Bit Name Initial Value 7 — IICX1 0 5 ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 3 FLSHE 0 2 — ICKS1 0 0 ICKS0 0 3.3 Operating Mode Descriptions 3.3.1 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. ...
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Mode 3 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. The CPU can access a 56-kbyte address space in mode 3. After a reset, the LSI is set to single-chip mode. ...
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Section 3 MCU Operating Modes 3.4 Address Map in Each Operating Mode Figures 3.1 and 3.2 show the address map in each operating mode. ROM: 256 kbytes, RAM: 10 kbytes Mode 2 (EXPE = 1) Advanced mode Extended mode with ...
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ROM: 56 kbytes, RAM: 4 kbytes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM H'0000 On-chip ROM H'DFFF External address space H'E080 On-chip RAM * H'EFFF External address space H'F800 Internal I/O registers 3 H'FE3F H'FE40 ...
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Section 3 MCU Operating Modes Rev. 3.00 Jan 25, 2006 page 64 of 872 REJ09B0286-0300 ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Exception Source Reset Reserved ...
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Exception Source External interrupt KIN7 to KIN0 External interrupt KIN9, KIN8 Reserved for system use External interrupt WUE15 to WUE8 Internal interrupt * External interrupt IRQ8 External interrupt IRQ9 External interrupt IRQ10 External interrupt IRQ11 External interrupt IRQ12 External interrupt ...
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Section 4 Exception Handling 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers ...
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Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, ...
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Section 4 Exception Handling The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from specified in the instruction code. Table 4.3 shows the status of CCR after execution ...
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Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should ...
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Section 4 Exception Handling Rev. 3.00 Jan 25, 2006 page 72 of 872 REJ09B0286-0300 ...
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Section 5 Interrupt Controller 5.1 Features Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). Priorities settable with ICR An interrupt control ...
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Section 5 Interrupt Controller SYSCR NMIEG NMI input IRQ input KIN input WUE input Internal interrupt sources SWDTEND to MMCIC Interrupt controller Legend: : Interrupt control register ICR : IRQ sense control register ISCR : IRQ enable register IER : ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol I/O NMI Input IRQ15 to IRQ0 Input ExIRQ15 to ExIRQ2 KIN9 to KIN0 Input WUE15 to WUE8 Input 5.3 Register Descriptions The interrupt ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers (ICRA to ICRD) The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence between interrupt sources and ICRA to ICRD settings is shown in table ...
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Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set address break is requested. Bit Bit Name Initial Value 7 CMIF Undefined 6 — All 0 ...
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Section 5 Interrupt Controller 5.3.3 Break Address Registers (BARA to BARC) The BAR registers specify an address that break address. An address in which the first byte of an instruction exists should be ...
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IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2. Switching between pins IRQ15 to IRQ2 and pins ExIRQ15 to ...
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Section 5 Interrupt Controller ISCRH Bit Bit Name Initial Value 7 IRQ7SCB 0 6 IRQ7SCA 0 5 IRQ6SCB 0 4 IRQ6SCA 0 3 IRQ5SCB 0 2 IRQ5SCA 0 1 IRQ4SCB 0 0 IRQ4SCA 0 ISCRL Bit Bit Name Initial Value ...
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IRQ Enable Registers (IER16, IER) IERs control the enabling and disabling of interrupt requests IRQ15 to IRQ0. IER16 Bit Bit Name Initial Value 15 IRQ15E 0 14 IRQ14E 0 13 IRQ13E 0 12 IRQ12E 0 11 IRQ11E 0 10 ...
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Section 5 Interrupt Controller 5.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. ISR16 Bit Bit Name Initial Value 7 IRQ15F 0 6 IRQ14F 0 5 IRQ13F ...
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Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6) Wake-Up Event Interrupt Mask Register (WUEMR3) The KMIMR and WUEMR registers enable or disable wake-up key-sensing interrupt inputs (KIN9 to KIN0), and wake-up event interrupt inputs (WUE15 to WUE8). KMIMRA Bit Bit ...
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Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are four external interrupts: NMI, IRQ15 to IRQ0, KIN9 to KIN0 and WUE15 to WUE8. These interrupts can be used to restore this LSI from software standby mode. NMI ...
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IRQnSCA, IRQnSCB detection circuit IRQn input or ExIRQn* input Notes ExIRQn stands for ExIRQ15 to ExIRQ2. Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 KIN9 to KIN0 Interrupts, WUE15 to WUE8 Interrupts: Interrupts ...
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Section 5 Interrupt Controller KMIMn KINn input Note Figure 5.3 Block Diagram of Interrupts KIN9 to KIN0 and WUE15 to WUE8 5.4.2 Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following ...
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Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source Name External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DTC SWDTEND (Software activation data transfer end) WDT_0 WOVI0 (Interval timer) WDT_1 WOVI1 (Interval timer) ...
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Section 5 Interrupt Controller Origin of Interrupt Source Name FRT ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) Reserved for system use ...
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Origin of Interrupt Source Name SCI_2 ERI2 (Reception error 2) RXI2 (Reception completion 2) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) IIC_0 IICC0 IICM0 IICR0 IICT0 IIC_1 IICC1 IICM1 IICR1 IICT1 — Reserved for system use — Reserved ...
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Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break ...
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Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.5 shows the ...
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Section 5 Interrupt Controller Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode Setting Interrupt Control Mode INTM1 INTM0 Legend: O: Interrupt operation control performed IM: Used as an interrupt mask bit PR: Sets ...
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The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. An interrupt with interrupt control level ...
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Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the ...
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Figure 5.7 shows a flowchart of the interrupt acceptance operation interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. 2. According to the interrupt ...
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Section 5 Interrupt Controller An interrupt with interrupt control level 1? IRQ0 Yes Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt 5.6.3 Interrupt Exception Handling Sequence Figure 5.8 shows the interrupt exception handling sequence. The example shown ...
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Figure 5.8 Interrupt Exception Handling Section 5 Interrupt Controller Rev. 3.00 Jan 25, 2006 page 97 of 872 REJ09B0286-0300 ...
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Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.7 shows interrupt response times—the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.7 ...
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DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: Interrupt request to CPU Activation request to DTC Both of the above For details of interrupt requests that can ...
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Section 5 Interrupt Controller Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.9 summarizes interrupt source ...
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Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to ...
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Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. ...
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Section 6 Bus Controller This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. The BSC also has a bus arbitration function, and controls the operation ...
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Section 6 Bus Controller Note: * CompactFlash (CompactFlash States, licensed through CFA (CompactFlash External bus control signals WAIT/CPWAIT Figure 6.1 Block Diagram of Bus Controller Rev. 3.00 Jan 25, 2006 page 104 of 872 REJ09B0286-0300 trademark ...
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Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Pin Configuration Symbol I/O AS Output IOS Output CPCS1, CPCS2 Output CS256 Output RD/CPOE Output HWR/CPWE Output LWR Output WAIT/CPWAIT Input Function Strobe signal indicating that ...
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Section 6 Bus Controller 6.3 Register Descriptions The bus controller has the following registers. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). Bus control register (BCR) Bus control register 2 (BCR2) Wait state control ...
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Bit Bit Name Initial Value 4 BRSTS1 1 3 BRSTS0 0 2 CFE 0 1 IOS1 1 0 IOS0 1 R/W Description R/W Burst Cycle Select 1 Selects the number of states in the burst cycle of the burst ROM ...
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Section 6 Bus Controller 6.3.2 Bus Control Register 2 (BCR2) BCR2 is used to specify the access mode for the CP expansion area (basic mode) and CF expansion area (memory card mode). Bit Bit Name Initial Value 7 OWEAC 0 ...
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Bit Bit Name Initial Value 4 ASTCP 1 3 ADFULLE 0 2 EXCKS 0 1 BUSDIVE 1 0 CPCSE 0 R/W Description R/W CP/CF Expansion Area Access State Control Selects the number of states for access to the CP/CF expansion ...
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Section 6 Bus Controller 6.3.3 Wait State Control Register (WSCR) WSCR is used to specify the data bus width for external address space access, the number of access states, the wait mode, and the number of wait states for access ...
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Bit Bit Name Initial Value 4 AST 1 3 WMS21 0 2 WMS20 0 1 WC1 1 0 WC0 1 R/W Description R/W Access State Control Selects the number of states for access to the basic expansion area. This bit ...
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Section 6 Bus Controller 6.3.4 Wait State Control Register 2 (WSCR2) WSCR2 is used to specify the wait mode and number of wait states in access to the 256-kbyte expansion area and CP/CF expansion area. Bit Bit Name Initial Value ...
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Bit Bit Name Initial Value 2 WC22 1 1 WC21 1 0 WC20 1 6.4 Bus Control 6.4.1 Bus Specifications The external address space bus specifications consist of three elements: Bus width, the number of access states, and the wait ...
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Section 6 Bus Controller Wait Mode and Number of Program Wait States: When a 3-state access space is designated by the AST bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is ...
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Table 6.2 Address Ranges and External Address Spaces Address Range H'080000–H'F7FFFF (15 Mbytes) H'F80000–H'FBFFFF (256 kbytes) 256-kbyte expansion area H'FC0000–H'FEFFFF (192 kbytes) H'FF0800–H'FF7FFF H'FF8000–H'FFBFFF (16 kbytes) H'FFC000–H'FFCFFF (4 kbytes) CP expansion area (1), CF expansion area H'FFD000–H'FFDFFF (4 kbytes) CP ...
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Section 6 Bus Controller Address Range H'(FF)F000–H'(FF)F7FF (2 kbytes) H'(FF)FF00–H'(FF)FF7F (128 bytes) Legend: : This address range unconditionally becomes the basic expansion area when it is accessed. : Condition for making this address range included in the basic expansion area ...
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Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface BRSTRM CS256E CPCSE CFE — — — — ...
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Section 6 Bus Controller Table 6.4 Bus Specifications for Basic Expansion Area/Basic Bus Interface ABW AST WMS1 WMS0 0 0 — — Other than WMS1 = 0 and WMS0 = — — ...
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Table 6.5 Bus Specifications for 256-kbyte Expansion Area/Basic Bus Interface ABW256 AST256 WMS10 0 0 — — Legend: : Don’t care WC11 WC10 Bus Width — — 16 — — ...
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Section 6 Bus Controller Table 6.6 Bus Specifications for CP Expansion Area (Basic Mode)/Basic Bus Interface ABWCP ASTCP WMS21 0 0 — Other than WMS21 = 0 and WMS20 = — Other than ...
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Table 6.7 Bus Specifications for CF Expansion Area (Memory Card Mode)/Basic Bus Interface ASTCP WMS21 WMS20 0 — — Other than WMS21 = 0 and WMS20 = 1 or WMS21 = 1 and WMS20 = 1 Legend: ...
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Section 6 Bus Controller 6.4.3 Normal Mode The external address space is initialized as the basic bus interface and a 3-state access space. In mode 3 (normal mode), the address space other than on-chip ROM, on-chip RAM, internal I/O registers, ...
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Basic Bus Interface The basic bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications for the basic expansion area, 256-kbyte expansion area, and CP/CF expansion area when using the basic bus ...
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Section 6 Bus Controller Byte size • Even address Byte size • Odd address Word size Longword size Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes Table 6.9 shows the data buses used and ...
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Basic Operation Timing 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait ...
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Section 6 Bus Controller 8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait ...
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Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and ...
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Section 6 Bus Controller Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS (IOSE = D15 to D8 Read HWR LWR Write D15 to ...
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Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS * (IOSE = 0) RD D15 to D8 Read HWR LWR Write D15 ...
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Section 6 Bus Controller 16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used ...
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Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS * (IOSE = 0) RD D15 to D8 Read HWR LWR Write D15 ...
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Section 6 Bus Controller Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS * (IOSE = 0) RD D15 to D8 Read HWR LWR Write D15 to ...
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Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait states (T ). There are three ways of inserting wait states: Program wait insertion, pin W wait insertion ...
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Section 6 Bus Controller WAIT/CPWAIT Address bus AS/IOS (IOSE = 0) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS * (IOSE = 0) RD Read Data bus WR Write Data bus Notes: ↓ shown in clock indicates the WAIT/CPWAIT ...
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Basic Operation Timing The number of access states in the initial cycle (full access) of the burst ROM interface is determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be ...
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Section 6 Bus Controller Address bus AS/IOS (IOSE = 0) RD Data bus Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control As with the basic bus interface, program wait insertion or ...
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Memory Card Interface A CP expansion area can be set to the CF expansion area (memory card mode) by setting both the CPCSE bit in BCR2 to 1 and the CFE bit in BCR memory card ...
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Section 6 Bus Controller 6.7.2 Valid Strobes Table 6.10 shows the data buses used and valid strobes. Table 6.10 Data Buses Used and Valid Strobes Access Read/ Size Write Address Byte Read Even Odd Write Even Odd Word Read — ...
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Address bus CPCS1, CPCS2 CPOE Read D15 to D0 CPWE Write D15 to D0 Figure 6.17 Access Timing in Memory Card Mode (Basic Cycle Address bus CPCS1, CPCS2 CPOE Read D15 to D0 CPWE Write D15 to D0 ...
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Section 6 Bus Controller 6.7.4 Wait Control With memory card interface, there are two ways of inserting wait states: Program wait insertion and pin wait insertion using the CPWAIT pin. Program Wait Mode: A specified number of wait states T ...
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Idle Cycle When this LSI accesses the external address space, it can insert a 1-state idle cycle (T bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for ...
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Section 6 Bus Controller Table 6.11 shows the pin states in an idle cycle. Table 6.11 Pin States in Idle Cycle Pins A17 to A0 D15 to D0 AS, IOS, CS256, CPCS1, CPCS2 RD, CPOE HWR, LWR, CPWE 6.9 Bus ...
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Bus Transfer Timing When a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. ...
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Section 6 Bus Controller Rev. 3.00 Jan 25, 2006 page 144 of 872 REJ09B0286-0300 ...
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Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information ...
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Section 7 Data Transfer Controller (DTC) Interrupt controller Interrupt request CPU interrupt request Legend: MRA, MRB : DTC mode register A, B CRA, CRB : DTC transfer count register A, B SAR : DTC source address register DAR : DTC ...