M30873FHGP#U3 Renesas Electronics America, M30873FHGP#U3 Datasheet - Page 444

• Manufacturer Part Number: M30873FHGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 420 of 587
23.1.11.1 Message Slot for Transmit Operation
23.1.11.2 Message Slot for Receive Operation
When using the CAN interrupt, the CiSISTR register (i = 0, 1) indicates which message slot has requested an
interrupt. The SISj bit (j = 0 to 15) is not automatically set to 0 (interrupt not requested) even if the interrupt is
acknowledged. Set the SISj bit to 0 by a program.
Use the MOV instruction to set the SISj bits to 0. Write a 0 to the bit which is to set to 0, and write a 1 to the bit
which is to remain unchanged.
Refer to 23.4 CAN Interrupts for details.
The SISj bit becomes 1 (interrupt requested) when the value of the CiTSR register is stored into the message
slot j after a transmit operation is completed.
The SISj bit becomes 1 (interrupt requested) when the receive message is stored in the message slot j after a
receive operation is completed.
NOTES:
1. If the RSPLOCK bit in registers CiMCTL0 to CiMCTL15 is set to 0 (automatic answering to the remote
2. In the remote frame transmit message slot, the SISj bit becomes 1 both when the remote frame transmit
3. If an interrupt generation (the SISj bit becomes 1) and writing a 0 to the SISj bit by a program occur
4. Regardless of whether the SIMj bit in the CiSIMKR register is set to 0 (interrupt request masked) or to 1
frame enabled), the SISj bit becomes 1 both when the remote frame receive operation is completed and
when the following data frame transmit operation is completed.
operation is completed and when the data frame receive operation is completed.
simultaneously, the SISj bit becomes 1.
(interrupt request enabled), the SISj bit becomes 1 at the completion of the transmit operation or at the
completion of the receive operation.
For example: To set the SIS0 bit in CAN0 to 0
mov.w #07FFFh, C0SISTR
23. CAN Module