HD6473837HV Renesas Electronics America, HD6473837HV Datasheet - Page 292

• Manufacturer Part Number: HD6473837HV
• Description: MCU 3/5V 60K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473837HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 84
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
Serial data is transmitted from pin TXD using the communication format outlined in
table 10.16. Next, TDRE is checked as the stop bit is being transmitted.
If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of
the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent
the output remains at 1 (mark state). A TEI interrupt is requested in this state if bit TEIE in SCR3
is set to 1.
Figure 10.13 shows a typical operation in asynchronous transmission mode.
Receiving: Figure 10.14 shows a typical flow chart for receiving serial data. After SCI3
initialization, follow the procedure below.
Serial
data
TDRE
TEND
SCI3
operation
User
processing
TXI request
1
Figure 10.13 Typical Transmit Operation in Asynchronous Mode
Start
bit
0
TDRE cleared to 0
Write data in TDR
D0
(8-Bit Data, Parity Bit Added, and 1 Stop Bit)
D1
Transmit
data
1 frame
D7
Parity
bit
TXI request
0/1
Stop
bit
1
Start
bit
0
D0
D1
Transmit
data
1 frame
D7
Parity
bit
TEI request
0/1
Stop
bit
1
Mark
state
1
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