M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 73

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ03B0003-0240
Under development
This document is under development and its contents are subject to change.
Figure 5.19 Timing Diagram (7)
Memory Expansion Mode and Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplexed bus selection)
Read timing
Write timing
Measuring conditions :
tcyc =
Aug 25, 2006
VCC = 5 V
Input timing voltage : V
Output timing voltage : V
WR,WRL,
WRH
BCLK
BCLK
CSi
BHE
f(BCLK)
ADi
/DBi
ADi
/DBi
ADi
ALE
CSi
BHE
ADi
ALE
RD
1
t
d(BCLK-ALE)
page 71 of 88
t
d(BCLK-CS)
t
d(BCLK-ALE)
(0.5 ✕ tcyc-25)ns.min
25ns.max
t
t
t
25ns.max
t
25ns.max
t
d(BCLK-AD)
d(BCLK-CS)
d(AD-ALE)
25ns.max
d(BCLK-AD)
(0.5 ✕ tcyc-25)ns.min
d(AD-ALE)
25ns.max
25ns.max
IL
OL
= 0.8 V, V
Address
= 0.4 V, V
Address
t
t
h(BCLK-ALE)
h(BCLK-ALE)
-4ns.min
-4ns.min
IH
OH
= 2.0 V
= 2.4 V
t
d(BCLK-RD)
t
(0.5 ✕ tcyc-15)ns.min
d(BCLK-DB)
t
h(ALE-AD)
t
40ns.max
25ns.max
25ns.max
d(BCLK-WR)
t
d(AD-WR)
t
0ns.min
d(AD-RD)
0ns.min
t
dZ(RD-AD)
8ns.max
tcyc
tcyc
(1.5 ✕ tcyc-40)ns.min
(1.5 ✕ tcyc-45)ns.max
Data output
t
d(DB-WR)
t
ac3(RD-DB)
5. Electric Characteristics (Normal-ver.)
Data input
t
SU(DB-RD)
40ns.min
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-10)ns.min
t
t
h(RD-CS)
h(BCLK-WR)
t
(0.5 ✕ tcyc-10)ns.min
h(BCLK-RD)
(0.5 ✕ tcyc-10)ns.min
t
(0.5 ✕ tcyc-10)ns.min
h(WR-CS)
t
0ns.min
0ns.min
t
t
h(RD-AD)
t
h(RD-DB)
h(WR-AD)
h(WR-DB)
0ns.min
t
t
h(BCLK-AD)
h(BCLK-AD)
t
h(BCLK-CS)
t
4ns.min
t
4ns.min
4ns.min
h(BCLK-CS)
4ns.min
VCC = 5 V
h(BCLK-DB)
4ns.min
Address
Address