M30620FCAFP#U5 Renesas Electronics America, M30620FCAFP#U5 Datasheet - Page 35
M30620FCAFP#U5
Manufacturer Part Number
M30620FCAFP#U5
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.M30622SAFPU5.pdf
(277 pages)
2.M30622SAFPU5.pdf
(617 pages)
3.M30622SAFPU5.pdf
(308 pages)
Specifications of M30620FCAFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Package
100PQFP
Family Name
M16C
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
87
Interface Type
SIM/UART
On-chip Adc
10-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCAFP#U5M30620FCAFP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bus Control
32
Table 1.9.6. Microcomputer status in hold state
Figure 1.9.5. Bus-using priorities
Table 1.9.7. External bus status when the internal area is accessed
__________
Oscillation
R/W signal, address bus, data bus, CS, BHE
Programmable I/O ports
HLDA
Internal peripheral circuits
ALE signal
(6) Hold signal
(7) External bus status when the internal area is accessed
Item
Address bus
Data bus
RD, WR, WRL, WRH
BHE
CS
ALE
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.9.6
shows the microcomputer status in the hold state.
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
Table 1.9.7 shows the external bus status when the internal area is accessed.
___
__________
When read
When write
Item
SFR accessed
Address output
Floating
Output data
RD, WR, WRL, WRH output
BHE output
Output “H”
Output “L”
P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
__________
_____
__________
HOLD > DMAC > CPU
_______
__________
ON
Floating
Floating
Maintains status when hold signal is received
Output “L”
ON (but watchdog timer stops)
Undefined
Internal ROM/RAM accessed
Maintain status before accessed
address of external area
Floating
Undefined
Output “H”
Maintain status before accessed
status of external area
Output “H”
Output “L”
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status
__________
M16C / 62A Group
Mitsubishi microcomputers
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