DF2168VTE33 Renesas Electronics America, DF2168VTE33 Datasheet - Page 600
![MCU FLASH 3V 256K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2168VTE33
Manufacturer Part Number
DF2168VTE33
Description
MCU FLASH 3V 256K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2168VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2168VTE33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 600 of 876
- Download datasheet (5Mb)
Note:
16.3.22 BT Control Status Register 1 (BTCSR1)
BTCSR1 is one of the registers used to implement the BT mode. The BTCSR1 register contains
the bits used to enable or disable interrupts to the slave (this LSI). The IBFI3 interrupt is enabled
by setting the IBFIE3 bit in HICR2 to 1.
Rev. 3.00, 03/04, page 558 of 830
Bit Bit Name Initial Value Slave Host Description
1
0
Bit Bit Name
7
6
5
HBTWIE
HBTRIE
RSTRENBL 0
HRSTIE
IRQCRIE
*
Don't care.
0
0
0
0
Initial Value Slave Host Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BTDTR Host Write Start Interrupt Enable
Enables or disables the HBTWI interrupt which is an
IBFI3 interrupt source to the slave.
0: BTDTR host write start interrupt is disabled.
1: BTDTR host write start interrupt is enabled.
BTDTR Host Read End Interrupt Enable
Enables or disables the HBTRI interrupt which is an
IBFI3 interrupt source to the slave.
0: BTDTR host read end interrupt is disabled.
1: BTDTR host read end interrupt is enabled.
Slave Reset Read Enable
The host reads 0 from the BMC_HWRST bit in
BTIMSR. When this bit is set to 1, the host can read
1 from the BMC_HWRST bit.
0: Host always reads 0 from BMC_HWRST
1: Host can reads 0 from BMC_HWRST
BT Reset Interrupt Enable
Enables or disables the HRSTI interrupt which is an
IBFI3 interrupt source to the slave.
0: BT reset interrupt is disabled.
1: BT reset interrupt is enabled.
B2H_IRQ Clear Interrupt Enable
Enables or disables the IRQCRI interrupt which is
an IBFI3 interrupt source to the slave.
0: B2H_IRQ clear interrupt is disabled.
1: B2H_IRQ clear interrupt is enabled.
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