M30620FCAFP#U3 Renesas Electronics America, M30620FCAFP#U3 Datasheet - Page 275
M30620FCAFP#U3
Manufacturer Part Number
M30620FCAFP#U3
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.M30622SAFPU5.pdf
(277 pages)
2.M30622SAFPU5.pdf
(617 pages)
3.M30622SAFPU5.pdf
(308 pages)
Specifications of M30620FCAFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCAFP#U3M30620FCAFP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Chapter 5
Figure 5.3.3 Operations to save registers
[SP]–5
(Odd address)
[SP]–4
(Even address)
[SP]–3
(Odd address)
[SP]–2
(Even address)
[SP]–1
(Odd address)
[SP]
(Even address)
The register save operation performed in an interrupt sequence differs depending on whether the con-
tent of the stack pointer (SP)
If the stack pointer (SP)
counter (PC) each are saved simultaneously all 16 bits together. If the stack pointer indicates an odd
number, the register contents each are saved in two operations 8 bits at a time. Figure 5.3.3 shows how
registers are saved in each case.
*1 Stack pointer indicated by the U flag.
(1) When stack pointer (SP) contains an even number
*
Address
[SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After the microcomputer finishes saving registers, the SP content is [SP] minus 4.
Flag register
Program counter (PC
Program counter (PC
Flag register (FLG
Interrupt
(FLG
Stack area
H
)
Program counter
(PC
*1
L
)
H
indicates an even number, the contents of the flag register (FLG) and program
)
L
M
)
)
*1
Sequence in which order
registers are saved
Finished saving registers
in two operations.
is an even or an odd number when an interrupt request is acknowledged.
(1) Saved simul-
taneously, all 16
bits together
(2) Saved simul-
taneously, all 16
bits together
257
[SP]
(Odd address)
[SP]–5
(Even address)
[SP]–4
(Odd address)
[SP]–3
(Even address)
[SP]–2
(Odd address)
[SP]–1
(Even address)
(2) When stack pointer (SP) contains an odd number
Address
Program counter (PC
Program counter (PC
Flag register (FLG
Flag register
(FLG
Stack area
H
)
Program counter
(PC
L
)
H
)
L
M
)
)
Sequence in which order
registers are saved
Finished saving registers in
four operations.
5.3 Interrupt Sequence
(3)
(4)
(1)
(2)
Saved
separately, 8
bits at a time
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