SAF-XC878-13FFI 5V AA Infineon Technologies, SAF-XC878-13FFI 5V AA Datasheet - Page 113
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SAF-XC878-13FFI 5V AA
Manufacturer Part Number
SAF-XC878-13FFI 5V AA
Description
IC MCU 8BIT FLASH 64-LQFP
Manufacturer
Infineon Technologies
Series
XC8xxr
Specifications of SAF-XC878-13FFI 5V AA
Core Processor
XC800
Core Size
8-Bit
Speed
27MHz
Connectivity
SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
52KB (52K x 8)
Program Memory Type
FLASH
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000447274
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3.23
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
•
•
•
•
Features
•
•
•
•
•
The OCDS functional blocks are shown in
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals.
After processing memory address and control signals from the core, the MMC provides
proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and
a Monitor RAM (for work-data and Monitor-stack).
The OCDS system is accessed through the JTAG
exclusively for testing and debugging activities and is not normally used in an
application. The dedicated MBC pin is used for external configuration and debugging
control.
Note: All the debug functionality described here can normally be used only after XC87x
1) The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports
Data Sheet
(Ports 1 and 2/Port 5).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Use the built-in debug functionality of the XC800 Core
Add a minimum of hardware overhead
Provide support for most of the operations by a Monitor Program
Use standard interfaces to communicate with the Host (a Debugger)
Set breakpoints on instruction address and on address range within the Program
Memory
Set breakpoints on internal RAM address range
Support unlimited software breakpoints in Flash/RAM code region
Process external breaks via JTAG and upon activating a dedicated pin
Step through the program code
has been started in OCDS mode.
On-Chip Debug Support
106
Figure
33. The Monitor Mode Control (MMC)
1)
, which is an interface dedicated
Functional Description
XC87xCLM
V1.5, 2011-03
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