UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 131
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Data memory
space
Notes 1. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack memory.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.7 Security Setting).
Program
memory
space
When boot swap is used:
Furthermore, the areas of FDF00H to FE2FFH also cannot be used with the
F F F F F H
F F F 0 0 H
F F E F F H
F F E E 0 H
F F E D F H
F D F 0 0 H
F D E F F H
F 1 0 0 0 H
F 0 F F F H
F 0 8 0 0 H
F 0 7 F F H
F 0 0 0 0 H
E F F F F H
2 0 0 0 0 H
1 F F F F H
0 0 0 0 0 H
General-purpose register
Special function register (2nd SFR)
Special function register (SFR)
32 bytes
Flash memory
RAM
Reserved
Reserved
Figure 4-7. Memory Map (
256 bytes
51.75 KB
128 KB
Mirror
8 KB
2 KB
Notes 1, 2
IDs to 000C4H to 000CDH.
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
μ
PD78F1012, 78F1014)
0 1 0 C 3 H
0 0 0 C E H
0 0 0 C D H
0 0 0 C 4 H
0 0 0 C 0 H
0 0 0 B F H
0 0 0 8 0 H
0 0 0 7 F H
0 0 0 0 0 H
1 F F F F H
0 1 0 C E H
0 1 0 C D H
0 1 0 C 4 H
0 1 0 C 0 H
0 1 0 B F H
0 1 0 8 0 H
0 1 0 7 F H
0 1 0 0 0 H
0 0 F F F H
0 0 0 C 3 H
CHAPTER 4 CPU ARCHITECTURE
On-chip debug security
On-chip debug security
Option byte area
Option byte area
ID setting area
ID setting area
CALLT table area
CALLT table area
Vector table area
Vector table area
Program area
Program area
128 bytes
128 bytes
64 bytes
64 bytes
10 bytes
10 bytes
4 bytes
4 bytes
μ
PD78F1012 and 78F1014.
Note 3
Note 3
Note 3
Note 3
0 1 F F F H
Boot cluster 0
Boot cluster 1
Note 4
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