SAK-C167CR-L33M HA+ Infineon Technologies, SAK-C167CR-L33M HA+ Datasheet - Page 48

• Manufacturer Part Number: SAK-C167CR-L33M HA+
• Description: IC MCU 16BIT 2KB XRAM MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C167CR-L33M HA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 33.0 MHz
• Sram (incl. Cache): 4.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 16
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: K167CRL33MHAZNP; K167CRL33MHAZXP; SAKC167CRL33MHA; SP000017997; SP000103460; SP000103461

C167CR
C167SR
Functional Description
3.13
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
f
In direct drive mode the PLL base frequency is used directly (
= 2 … 5 MHz).
CPU
f
In prescaler mode the PLL base frequency is divided by 2 (
= 1 … 2.5 MHz).
CPU
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
The oscillator watchdog can be disabled via hardware by (externally) pulling low pin
OWE (internal pull-up provides high level if not connected). In this case (OWE = ‘0’) the
PLL remains idle and provides no clock signal, while the CPU clock signal is derived
directly from the oscillator clock or via prescaler. Also no interrupt request will be
generated in case of a missing oscillator clock.
Data Sheet
46
V3.3, 2005-02