SAK-C167CR-L33M HA+ Infineon Technologies, SAK-C167CR-L33M HA+ Datasheet - Page 69

• Manufacturer Part Number: SAK-C167CR-L33M HA+
• Description: IC MCU 16BIT 2KB XRAM MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C167CR-L33M HA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 33.0 MHz
• Sram (incl. Cache): 4.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 16
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: K167CRL33MHAZNP; K167CRL33MHAZXP; SAKC167CRL33MHA; SP000017997; SP000103460; SP000103461

upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
P0.15-13 (P0H.7-5).
Table 15
generation mode.
Table 15
CLKCFG
(P0H.7-5)
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
1) The external clock input range refers to a CPU clock range of 10 … 33 MHz (PLL operation).
2) The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
the duration of an individual TCL) is defined by the period of the input clock
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
=
to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency
does not change abruptly.
Due to this adaptation to the input clock the frequency of
it is locked to
duration of individual TCLs.
Data Sheet
f
OSC
× F). With every F’th transition of
associates the combinations of these three bits with the respective clock
CPU Frequency
f
f
f
f
f
f
f
f
f
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
CPU
C167CR Clock Generation Modes
f
OSC
× 4
× 3
× 2
× 5
× 1
× 1.5
/ 2
× 2.5
f
=
CPU
. The slight variation causes a jitter of
f
OSC
is half the frequency of
× F
f
OSC
External Clock
Input Range
2.5 to 8.25 MHz
3.33 to 11 MHz
5 to 16.5 MHz
2 to 6.6 MHz
1 to 33 MHz
6.66 to 22 MHz
2 to 66 MHz
4 to 13.2 MHz
for any TCL.
f
OSC
67
the PLL circuit synchronizes the CPU clock
1)
f
OSC
and the high and low time of
Notes
Default configuration
–
–
–
Direct drive
–
CPU clock via prescaler
–
B
) the CPU clock is derived from
f
CPU
f
CPU
is constantly adjusted so
Electrical Parameters
2)
which also effects the
V3.3, 2005-02
f
OSC
C167CR
C167SR
f
CPU
.
f
(i.e.
CPU