SAK-TC1762-128F66HL AC Infineon Technologies, SAK-TC1762-128F66HL AC Datasheet - Page 32

• Manufacturer Part Number: SAK-TC1762-128F66HL AC
• Description: IC MCU 32BIT 1024KB FLSH 176LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1762-128F66HL AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 66.0 MHz
• Sram (incl. Cache): 52.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TC1762
Preliminary
Functional Description
3.4
Memory Protection System
The TC1762 memory protection system specifies the addressable range and read/write
permissions of memory segments available to the current executing task. The memory
protection system controls the position and range of addressable segments in memory.
It also controls the types of read and write operations allowed within addressable
memory segments. Any illegal memory access is detected by the memory protection
hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the
error. Thus, the memory protection system protects critical system functions against both
software and hardware errors. The memory protection hardware can also generate
signals to the Debug Unit to facilitate tracing illegal memory accesses.
There are two Memory Protection Register Sets in the TC1762, numbered 0 and 1,
which specify memory protection ranges and permissions for code and data. The
PSW.PRS bit field determines which of these is the set currently in use by the CPU. As
the TC1762 uses a Harvard-style memory architecture, each Memory Protection
Register Set is broken down into a Data Protection Register Set and a Code Protection
Register Set. Each Data Protection Register Set can specify up to four address ranges
to receive a particular protection modes. Each Code Protection Register Set can specify
up to two address ranges to receive a particular protection modes.
Each Data Protection Register Sets and Code Protection Register Sets determines the
range and protection modes for a separate memory area. Each set contains a pair of
registers which determine the address range (the Data Segment Protection Registers
and Code Segment Protection Registers) and one register (Data Protection Mode
Register) which determines the memory access modes that applies to the specified
range.
Data Sheet
28
V1.0, 2008-04