SAF-C167CS-L16M 3V CA+ Infineon Technologies, SAF-C167CS-L16M 3V CA+ Datasheet - Page 60

• Manufacturer Part Number: SAF-C167CS-L16M 3V CA+
• Description: IC MCU 16BIT ROM/LESS MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C167CS-L16M 3V CA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 11 KB
• Interface Type: ASC, CAN, SSC
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 16.0 MHz
• Sram (incl. Cache): 11.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: F167CSL16M3VCAZNT; F167CSL16M3VCAZXT; SAFC167CSL16M3VCAT; SP000017109; SP000103470

P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 11
generation mode.
Table 11
CLKCFG
(RP0H.7-5)
1)
2)
Prescaler Operation
When prescaler operation is configured (CLKCFG=001
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
the duration of an individual TCL) is defined by the period of the input clock
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
f
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
it is locked to
duration of individual TCLs.
Data Sheet
CPU
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
The external clock input range refers to a CPU clock range of 10 … 16 MHz.
The maximum frequency depends on the duty cycle of the external clock signal.
=
f
OSC
associates the combinations of these three bits with the respective clock
CPU Frequency
f
f
f
f
f
f
f
f
f
F). With every F’th transition of
CPU
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
C167CS-3V Clock Generation Modes
f
OSC
f
CPU
=
/ 2
. The slight variation causes a jitter of
f
4
3
2
5
1
1.5
2.5
OSC
is half the frequency of
F
f
OSC
External Clock
Input Range
2.5 to 4 MHz
3.33 to 5.33 MHz
5 to 8 MHz
2 to 3.2 MHz
1 to 16 MHz
6.66 to 10.66 MHz
2 to 32 MHz
4 to 6.4 MHz
for any TCL.
56
f
f
OSC
OSC
1)
the PLL circuit synchronizes the CPU
and the high and low time of
Notes
Default configuration
–
–
–
Direct drive
–
CPU clock via prescaler
–
B
) the CPU clock is derived from
f
CPU
f
CPU
is constantly adjusted so
which also effects the
2)
C167CS-L16M3V
Low Power
V1.0, 2001-10
f
OSC
f
CPU
.
(i.e.