SAK-C167CS-L40M CA+ Infineon Technologies, SAK-C167CS-L40M CA+ Datasheet - Page 26
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SAK-C167CS-L40M CA+
Manufacturer Part Number
SAK-C167CS-L40M CA+
Description
IC MCU 16BIT 40MHZ MQFP-144
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAK-C167CS-LM_CA.pdf
(81 pages)
Specifications of SAK-C167CS-L40M CA+
Core Processor
C166
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Type
ROMless
Ram Size
11K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144- BSQFP
Data Bus Width
16 bit
Data Ram Size
11 KB
Interface Type
1xUSART, 1xSSC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
9
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Packages
PG-MQFP-144
Max Clock Frequency
40.0 MHz
Sram (incl. Cache)
11.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
24
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
K167CSL40MCAZNP
K167CSL40MCAZXP
SAK-C167CS-L40M CA+
SAK-C167CS-L40MCAIN
SAKC167CSL40MCAXT
SP000103490
K167CSL40MCAZXP
SAK-C167CS-L40M CA+
SAK-C167CS-L40MCAIN
SAKC167CSL40MCAXT
SP000103490
The C167CS also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 4
time:
Table 4
Exception Condition
Reset Functions:
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
Class A Hardware Traps:
– Non-Maskable Interrupt
– Stack Overflow
– Stack Underflow
Class B Hardware Traps:
– Undefined Opcode
– Protected Instruction
– Illegal Word Operand
– Illegal Instruction
– Illegal External Bus
Reserved
Software Traps
– TRAP Instruction
Data Sheet
Fault
Access
Access
Access
shows all of the possible exceptions or error conditions that can arise during run-
Hardware Trap Summary
Trap
Flag
–
NMI
STKOF
STKUF
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
–
–
Trap
Vector
RESET
RESET
RESET
NMITRAP
STOTRAP
STUTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
–
–
22
Vector
Location
00’0000
00’0000
00’0000
00’0008
00’0010
00’0018
00’0028
00’0028
00’0028
00’0028
00’0028
[2C
3C
Any
[00’0000
00’01FC
in steps
of 4
H
H
H
]
–
H
H
H
H
H
H
H
H
H
H
H
H
H
]
–
Trap
Number
00
00
00
02
04
06
0A
0A
0A
0A
0A
[0B
0F
Any
[00
7F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
]
]
–
–
C167CS-4R
V2.2, 2001-08
C167CS-L
Trap
Priority
III
III
III
II
II
II
I
I
I
I
I
–
Current
CPU
Priority