PIC16C622/JW Microchip Technology, PIC16C622/JW Datasheet - Page 19
![IC MCU EPROM 2KX14 COMP 18CDIP](/photos/12/13/121351/150-18-cdip_sml.jpg)
PIC16C622/JW
Manufacturer Part Number
PIC16C622/JW
Description
IC MCU EPROM 2KX14 COMP 18CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16C622/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
EPROM, UV
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
18-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
PIC16C622/JWR
PIC16C622/JWR
PIC16C622/JWR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
4.2.2
The Special Function Registers are registers used by
the CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
TABLE 4-1:
2003 Microchip Technology Inc.
Address Name
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h-09h
0Ah
0Bh
0Ch
0Dh-1Eh Unimplemented
1Fh
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h-89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh-9Eh
9Fh
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown,
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
Unimplemented
PCLATH
INTCON
PIR1
CMCON
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
Unimplemented
PCLATH
INTCON
PIE1
Unimplemented
PCON
Unimplemented
VRCON
2: IRP & RP1 bits are reserved; always maintain these bits clear.
q = value depends on condition, shaded = unimplemented
SPECIAL FUNCTION REGISTERS
normal operation.
SPECIAL REGISTERS FOR THE PIC16C62X
Addressing this location uses contents of FSR to address data memory (not a physical
register)
Timer0 Module’s Register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Addressing this location uses contents of FSR to address data memory (not a physical
register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
TRISB7
C2OUT
RBPU
VREN
IRP
IRP
Bit 7
RB7
GIE
GIE
—
—
—
—
—
—
—
(2)
(2)
INTEDG
TRISB6
C1OUT
RP1
RP1
VROE
CMIF
CMIE
PEIE
PEIE
Bit 6
RB6
—
—
—
—
—
(2)
(2)
TRISB5
T0CS
Bit 5
T0IE
T0IE
VRR
RP0
RB5
RP0
—
—
—
—
—
—
—
—
Write buffer for upper 5 bits of program counter
Write buffer for upper 5 bits of program counter
TRISA4
TRISB4
T0SE
INTE
INTE
Bit 4
RA4
RB4
TO
TO
—
—
—
—
—
TRISA3
TRISB3
RBIE
RBIE
Bit 3
RA3
RB3
PSA
VR3
CIS
PD
PD
—
—
—
The Special Function Registers can be classified into
two sets (core and peripheral). The Special Function
Registers associated with the “core” functions are
described in this section. Those related to the operation
of the peripheral features are described in the section
of that peripheral feature.
TRISA2
TRISB2
Bit 2
T0IF
CM2
T0IF
RA2
RB2
PS2
VR2
—
—
—
Z
Z
TRISA1
TRISB1
Bit 1
INTF
INTF
POR
CM1
RA1
RB1
PS1
VR1
DC
DC
—
—
TRISA0
TRISB0
Bit 0
RBIF
RBIF
BOR
CM0
RA0
RB0
PS0
VR0
—
—
C
C
PIC16C62X
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---x 0000
xxxx xxxx
---0 0000
0000 000x
-0-- ----
00-- 0000
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
---0 0000
0000 000x
-0-- ----
---- --0x
000- 0000
POR Reset
Value on
—
—
—
—
—
DS30235J-page 17
xxxx xxxx
Value on all
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
---u 0000
uuuu uuuu
---0 0000
0000 000u
-0-- ----
00-- 0000
xxxx xxxx
1111 1111
0000 0000
000q quuu
uuuu uuuu
---1 1111
1111 1111
---0 0000
0000 000u
-0-- ----
---- --uq
000- 0000
RESETS
other
—
—
—
—
—
(1)