PIC17C756-33I/SP Microchip Technology, PIC17C756-33I/SP Datasheet - Page 110
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PIC17C756-33I/SP
Manufacturer Part Number
PIC17C756-33I/SP
Description
MICRO CTRL 16K MEMORY OTP 64SDIP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-33I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-SDIP (0.750", 19.05mm)
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
PIC17C756-33I/P
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756-33I/SP
Manufacturer:
OKI
Quantity:
6 270
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 110 of 321
- Download datasheet (3Mb)
14.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. Table 14-2 shows
the formula for computation of the baud rate for differ-
ent USART modes. These only apply when the USART
is in synchronous master mode (internal clock) and
asynchronous mode.
Given the desired baud rate and Fosc, the nearest inte-
ger value between 0 and 255 can be calculated using
the formula below. The error in baud rate can then be
determined.
TABLE 14-2:
X = value in SPBRG (0 to 255)
TABLE 14-3:
DS30264A-page 110
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used by the Baud Rate
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
SYNC
0
1
Address
13h, Bank 0
15h, Bank 0
17h, Bank 0
13h, Bank 4
15h, Bank 4
17h, Bank 4
USART Baud Rate Generator (BRG)
Generator.
Asynchronous
Synchronous
Mode
Name
RCSTA1
TXSTA1
SPBRG1
RCSTA2
TXSTA2
SPBRG2
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Baud rate generator register
Baud rate generator register
SPEN
CSRC
SPEN
CSRC
Bit 7
F
F
OSC
OSC
Baud Rate
Bit 6
RX9
RX9
TX9
TX9
/(64(X+1))
/(4(X+1))
SREN
TXEN
SREN
TXEN
Bit 5
Preliminary
CREN
CREN
SYNC
SYNC
Bit 4
Bit 3
—
—
—
—
Example 14-1 shows the calculation of the baud rate
error for the following conditions:
EXAMPLE 14-1: CALCULATING BAUD
Writing a new value to the SPBRG, causes the BRG
timer to be reset (or cleared), this ensures that the BRG
does not wait for a timer overflow before outputting the
new baud rate.
Desired Baud rate=Fosc / (64 (X + 1))
Error =
FERR
FERR
Bit 2
—
—
F
Desired Baud Rate = 9600
SYNC = 0
9600 =
X
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
=
=
OSC
OERR
OERR
= 16 MHz
=
9615
(Calculated Baud Rate - Desired Baud Rate)
(9615 - 9600) / 9600
0.16%
TRMT
TRMT
Bit 1
16000000 /(64 (X + 1))
25.042 = 25
RATE ERROR
Desired Baud Rate
RX9D
TX9D
RX9D
TX9D
Bit 0
1997 Microchip Technology Inc.
0000 -00x
0000 --1x
xxxx xxxx
0000 -00x
0000 --1x
xxxx xxxx
Value on
POR,
BOR
other resets
Value on all
0000 -00u
0000 --1u
uuuu uuuu
0000 -00u
0000 --1u
uuuu uuuu
(Note1)
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