PIC17C756-33I/L Microchip Technology, PIC17C756-33I/L Datasheet - Page 260
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C756-33I/L
Manufacturer Part Number
PIC17C756-33I/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-33I/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC17C756-33I/L
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 260 of 304
- Download datasheet (6Mb)
PIC17C7XX
FIGURE 20-19:
TABLE 20-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
DS30289B-page 260
Note 1: Maximum pin capacitance = 10 pF for all I
Param
D102
No.
110
Param
120
121
122
No.
†
RX/DT
2: A fast mode (400 KHz) I
3: C
4: Max specifications for these parameters are valid for falling edge only. Specs are characterized with R
TX/CK
Sym
Tbuf
pin
Data in “Typ” column is at 5V, 25 C unless otherwise stated.
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Parameter #102 + #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line is released.
is characterized with R
These are only valid for fast mode operation (V
C
TckH2dtV
TckRF
TdtRF
Cb
pin
b
b
=400pF for standard mode, 200pF for fast mode, and 10pF for 1MHz mode.
is specified to be from 10-400pF. The minimum specifications are characterized with C
Sym
Bus free time
Bus capacitive loading
SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
Clock out rise time and fall time
(Master mode)
Data out rise time and fall time
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
Characteristic
p
=R
2
120
C bus device can be used in a standard mode I
p
min. The minimum fall time specification (t
121
100 kHz mode
400 kHz mode
1 MHz mode
Characteristic
2
C pins.
(1)
DD
=4.5-5.5V) and where the SPM bit (SSPSTAT<7>) =1.)
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
121
Min
4.7
1.3
0.5
—
122
f
) is characterized with C
2
C bus system, but the parameter # 107
Min
Max
—
—
—
—
—
—
400
—
—
—
Typ†
—
—
—
—
—
—
Units
ms
ms
ms
pF
2000 Microchip Technology Inc.
b
Max
50
75
25
40
25
40
=10pF. The rise time spec (t
Time the bus must be free
before a new transmission
can start
b
=10pF,and R
Units
ns
ns
ns
ns
ns
ns
Conditions
p
=R
p
Conditions
min and
p
=R
p
250 ns
max.
r
)
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