PIC18C242/JW Microchip Technology, PIC18C242/JW Datasheet - Page 254

• Manufacturer Part Number: PIC18C242/JW
• Description: IC MCU EPROM 8KX16 A/D 28CDIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242/JW

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: EPROM, UV
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-CDIP (0.300", 7.62mm) Window
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PIC18CXX2
FIGURE 21-12:
TABLE 21-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
DS39026C-page 252
Param.
70
71
71A
72
72A
73
73A
74
75
76
78
79
80
Note 1: Requires the use of Parameter # 73A.
No.
Note:
(CKP = 0)
(CKP = 1)
SDI
SCK
SDO
SS
SCK
2: Only if Parameter # 71A and # 72A are used.
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
T
TscH2diL,
TscL2diL
TdoR
TdoF
TscR
TscF
TscH2doV,
TscL2doV
Refer to Figure 21-4 for load conditions.
B
Symbol
2
B
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS to SCK or SCK input
SCK input high time
(Slave mode)
SCK input low time
(Slave mode)
Setup time of SDI data input to SCK edge
Last clock edge of Byte1 to the 1st clock edge
of Byte2
Hold time of SDI data input to SCK edge
SDO data output rise time
SDO data output fall time
SCK output rise time
(Master mode)
SCK output fall time (Master mode)
SDO data output valid after
SCK edge
70
80
71
73
MSb IN
Characteristic
MSb
74
72
75, 76
Continuous
Single Byte
Continuous
Single Byte
PIC18CXXX
PIC18LCXXX
PIC18CXXX
PIC18LCXXX
PIC18CXXX
PIC18LCXXX
BIT6 - - - - - -1
BIT6 - - - -1
78
79
1.25T
1.25T
1.5T
Min
T
100
100
CY
40
40
CY
CY
—
—
—
—
—
—
—
—
LSb
79
CY
78
LSb IN
+ 40
+ 30
+ 30
Max Units
2001 Microchip Technology Inc.
100
25
45
25
25
45
25
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
(Note 1)
(Note 1)
(Note 2)