PIC18C252/JW Microchip Technology, PIC18C252/JW Datasheet - Page 153
![IC MCU 16x16 A/D 28CDIP](/photos/7/29/72984/150-28-cdip_sml.jpg)
PIC18C252/JW
Manufacturer Part Number
PIC18C252/JW
Description
IC MCU 16x16 A/D 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C252/JW
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
EPROM, UV
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
For Use With
XLT28XP - SOCKET TRANSITION ICE 28DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C252/JW
Manufacturer:
MICROCHIP
Quantity:
4 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 153 of 305
- Download datasheet (6Mb)
15.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 15-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 15-1. From this, the error in
baud rate can be determined.
EXAMPLE 15-1:
TABLE 15-1:
TABLE 15-2:
Legend: X = value in SPBRG (0 to 255)
TXSTA
RCSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
Desired Baud Rate
Solving for X:
Calculated Baud Rate
Error
2001 Microchip Technology Inc.
Name
SYNC
0
1
USART Baud Rate Generator
(BRG)
X
X
X
Baud Rate Generator Register
CSRC
SPEN
Bit 7
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
CALCULATING BAUD RATE ERROR
Bit 6
TX9
RX9
=
=
=
=
=
=
=
=
=
BRGH = 0 (Low Speed)
SREN
TXEN
(Calculated Baud Rate - Desired Baud Rate)
F
( (F
((16000000 / 9600) / 64) - 1
[25.042] = 25
16000000 / (64 (25 + 1))
9615
(9615 - 9600) / 9600
0.16%
Bit 5
OSC
OSC
OSC
/ (64 (X + 1))
/ Desired Baud rate) / 64 ) - 1
, the nearest
CREN
SYNC
Desired Baud Rate
Bit 4
ADDEN
Bit 3
OSC
OSC
—
/(64(X+1))
/(4(X+1))
BRGH
FERR
Bit 2
Example 15-1 shows the calculation of the baud rate
error for the following conditions:
• F
• Desired Baud Rate = 9600
• BRGH = 0
• SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
15.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
OSC
OERR
TRMT
Bit 1
= 16 MHz
SAMPLING
OSC
RX9D
TX9D
Bit 0
/(16(X + 1)) equation can reduce the
Baud Rate = F
BRGH = 1 (High Speed)
PIC18CXX2
0000 -010
0000 -00x
0000 0000
Value on
POR,
BOR
NA
OSC
DS39026C-page 151
/(16(X+1))
Value on all
0000 -010
0000 -00x
0000 0000
RESETS
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