AT91M43300-25CI Atmel, AT91M43300-25CI Datasheet
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AT91M43300-25CI
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AT91M43300-25CI Summary of contents
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... I/O Operating Voltage Range • -40°C to +85°C Operating Temperature Range • AT91M63200 in a 176-lead TQFP Package; AT91M43300 in a 144-ball BGA Package Description The AT91M63200 and AT91M43300 are members of the Atmel AT91 16/32-bit micro- controller family which is based on the ARM7TDMI processor core. ...
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Absolute Maximum Ratings* Operating Temperature (Industrial) .....-40 ° +85 ° C Voltage on Any Input Pin with Respect to Ground.......................-0.5V to +5.5V Maximum Operating Voltage (Core) .....................3.6V Maximum Operating Voltage (I/Os) ......................5.5V DC Output Current .............................................. ...
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Power Consumption The values in the following tables are measured values in the operating conditions indicated (i.e. V 3.3V or 1.8V ° ). They represent the power consumption on the V Table 1. Core Power Consumption Mode ...
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Conditions Environment Constraints The output delays are valid for a capacitive load shown in Figure 1. Figure 1. Output/Bidir Pad Capacitive Load Timing Results The output delays are for a capacitive load ...
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Clock Waveforms Table 5. Clock Waveform Parameters Symbol Parameter 1/(t ) Oscillator Frequency CP t Main Clock Period CP t High Time CH t Low Time CL t Rising Edge r t Falling Edge f Table 6. Clock Propagation Times ...
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AC Characteristics EBI Signals Relative to MCKI The following tables show timings relative to operating condition limits defined in Table 4. See Figure 3. Table 7. General Purpose EBI Signals Symbol Parameter EBI MCKI Falling to NUB Valid 1 EBI ...
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Table 9. EBI Read Signals Symbol Parameter EBI MCKI Falling to NRD Valid 13 EBI MCKI Rising to NRD Valid 14 EBI D0 - D15 in Setup before MCKI Falling 15 EBI D0 - D15 in Hold after MCKI Falling ...
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Figure 3. EBI Signals Relative to MCKI MCKI NCS A23 NWAIT NUB/NLB/A0 (1) NRD (2) NRD D0 - D15 read NWR (No Wait States) NWR (Wait States D15 to Write Notes: 1. Early Read Protocol ...
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Peripheral Signals Relative to MCKI USART Signals Table 10. USART Outputs Symbol Parameter US MCKI Rising to SCK Output 1 Rising/Falling US MCKI Rising to TXD Toggling 2 US SCK Output Falling to TXD Toggling 3 US SCK Input Falling ...
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Figure 4. USART Signals Relative to MCKI MCKI SCK Output SCK Input TXD RXD RXD/SCK (Asynchronous) AT91M63200/M43300 ...
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SPI Signals Table 14. SPI Signals in Master Mode Symbol Parameter t SPI Operating Period SPCK f SPI Operating Frequency SPCK SP Delay before NPCS[3: Delay between Chip Selects 2 SP Delay before SPCK 3 SP MISO/SPCK Setup ...
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Timer Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3 Waveform Event Detection mode and 4(t CP there are the following ...
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Figure 6. Timer Relative to MCKI MCKI TIOA/TIOB/TCLK Asynchronous In TC TCLK Synchronous Input TC 5H TIOA/TIOB Synchronous Inputs TC 1 TIOA Output TC TIOB Output 3(t /2) CP Detect ...
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Watchdog Timer Signals Table 19. Watchdog Timer Outputs Symbol Parameter WD MCKI Rising to NWDOVF Rising 1 WD MCKI Rising to NWDOVF Falling 2 Figure 7. Watchdog Signals Relative to MCKI MCKI NWDOVF Output Reset Signals Certain setup constraints must ...
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Advanced Interrupt Controller Signals The inputs can be used synchronously or asynchronously (in relation to MCKI). For synchronous AIC inputs, certain setup/hold constraints must be met. These constraints are shown in Table 22 and are represented in Figure 9. For ...
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Parallel I/O Signals Table 25. PIO Outputs Symbol Parameter PIO MCKI Falling to PIO Output Rising 1 PIO MCKI Falling to PIO Output Falling 2 The inputs can be used synchronously or asynchronously (in relation to MCKI). For synchronous PIO ...
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Multi-processor Interface Signals (AT91M63200 Only) Figure 11. External Arbitration MPI_BR MPI_BG MPI_D[15:0] Table 28. External Arbitration Symbol Parameter MPI_BR High to MPI_BG High Delay t 1 (30 pf) t MPI_BR Low to MPI_BG Low Data Transfer Minimum ...
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Table 29. MPI Read Access Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS t Output Enable to Output Valid Byte Select to Output Valid LB ...
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Table 30. MPI Write Access Symbol Parameter t Write Cycle Time WC t Address Valid to End of Write AW t Chip Select to End of Write CW t Write pulse-width Byte Select to End of Write ...
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Figure 14. MPI Write Access (MPI_NCS Controlled) MPI_A[9:1] MPI_RNW MPI_NCS MPI_NLB, MPI_NUB MPI_Din[15:0] Figure 15. MPI Write Access (MPI_NLB, MPI_NUB Controlled) MPI_A[9:1] MPI_RNW MPI_NCS MPI_NLB, MPI_NUB MPI_Din[15:0] AT91M63200/M43300 Valid Address ...
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