AT90S1200-12YC Atmel, AT90S1200-12YC Datasheet - Page 25

• Manufacturer Part Number: AT90S1200-12YC
• Description: IC MCU 1K FLSH 12MHZ 20SSOP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S1200-12YC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI
• Peripherals: POR, WDT
• Number Of I /o: 15
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Ram Size: -
• Data Converters: -

EEPROM Read/Write
Access
EEPROM Address Register –
EEAR
EEPROM Data Register –
EEDR
EEPROM Control Register –
EECR
0838H–AVR–03/02
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 2.5 - 4 ms, depending on the V
self-timing function, however, lets the user software detect when the next byte can be
written. If the user code contains code that writes the EEPROM, some precaution must
be taken. In heavily filtered power supplies, V
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. CPU operation under these condi-
tions is likely cause the program counter to perform unintentional jumps and eventually
execute the EEPROM write code. To secure EEPROM integrity, the user is advised to
use an external under-voltage reset circuit in this case.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to “EEPROM Control Register – EECR” on page 25 for details on this.
When the EEPROM is read or written, the CPU is halted for two clock cycles before the
next instruction is executed.
• Bit 7, 6 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and will always read as zero.
• Bits 5..0 – EEAR5..0: EEPROM Address
The EEPROM Address Register (EEAR5..0) specifies the EEPROM address in the 64-
byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
63.
• Bits 7..0 – EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to
the EEPROM in the address given by the EEAR register. For the EEPROM read opera-
tion, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and will always be read as zero.
Bit
$1E
Read/Write
Initial Value
Bit
$1D
Read/Write
Initial Value
Bit
$1C
Read/Write
Initial Value
MSB
R/W
R
R
7
–
0
7
0
7
–
0
R/W
R
R
6
–
0
6
0
6
–
0
EEAR5
R/W
R/W
R
5
0
5
0
5
–
0
EEAR4
R/W
R/W
R
4
0
4
0
4
–
0
CC
EEAR3
R/W
R/W
R
3
0
3
0
3
–
0
is likely to rise or fall slowly on Power-
EEAR2
R/W
R/W
R
2
0
2
0
2
–
0
EEAR1
EEWE
R/W
R/W
R/W
1
0
1
0
1
0
AT90S1200
EEAR0
EERE
LSB
R/W
R/W
R/W
CC
0
0
0
0
0
0
voltages. A
EEAR
EEDR
EECR
25