AT90S2333-8AI Atmel, AT90S2333-8AI Datasheet - Page 40
![IC MCU 2K 8MHZ A/D IT 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
AT90S2333-8AI
Manufacturer Part Number
AT90S2333-8AI
Description
IC MCU 2K 8MHZ A/D IT 32TQFP
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheet
1.AT90LS2333-4AC.pdf
(103 pages)
Specifications of AT90S2333-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Serial Peripheral Interface - SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S2333/4433 and
peripheral devices or between several AVR devices. The AT90S2333/4433 SPI features include the following:
• Full-Duplex, 3-Wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
Figure 36. SPI Block Diagram
The interconnection between master and slave CPUs with SPI is shown in Figure 37. The PB5(SCK) pin is the clock output
in the master mode and is the clock input in the slave mode. Writing to the SPI data register of the master CPU starts the
SPI clock generator, and the data written shifts out of the PB3(MOSI) pin and into the PB3(MOSI) pin of the slave CPU.
After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable
bit (SPIE) in the SPCR register is set, an interrupt is requested. The Slave Select input, PB2(SS), is set low to select an
individual slave SPI device. The two shift registers in the Master and the Slave can be considered as one distributed 16-bit
circular shift register. This is shown in Figure 37. When data is shifted from the master to the slave, data is also shifted in
the opposite direction, simultaneously. This means that during one shift cycle, data in the master and the slave are
interchanged.
AT90S/LS2333 and AT90S/LS4433
40
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