AT90S4434-8PC Atmel, AT90S4434-8PC Datasheet - Page 6

• Manufacturer Part Number: AT90S4434-8PC
• Description: IC MCU 4K FLSH 8MHZ A/D 40DIP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S4434-8PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D
converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following
those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The program
memory is executed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 2K/4K address space is directly accessed. Most AVR instructions
have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effec-
tively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The 9/10-bit stack pointer (SP) is read/write-accessible in the I/O space.
The 256/512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 3. Memory Maps
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-
gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
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AT90S/LS4434 and AT90S/LS8535
Program Memory
Program Flash
(2K/4K x 16)
$000
$7FF/$FFF
Working Registers
32 Gen. Purpose
64 I/O Registers
Internal SRAM
Data Memory
(256/512 x 8)
$015F/$025F
$0000
$001F
$0020
$005F
$0060
(256/512 x 8)
Data Memory
EEPROM
$000
$0FF/$1FF