AT90S8515-8PC Atmel, AT90S8515-8PC Datasheet - Page 10

IC MCU 8K FLSH 8MHZ 40DIP

AT90S8515-8PC

Manufacturer Part Number
AT90S8515-8PC
Description
IC MCU 8K FLSH 8MHZ 40DIP
Manufacturer
Atmel
Series
AVR® 90Sr

Specifications of AT90S8515-8PC

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-

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General-purpose
Register File
X-register, Y-register and
Z-register
10
AT90S8515
Figure 6 shows the structure of the 32 general-purpose working registers in the CPU.
Figure 6. AVR CPU General-purpose Working Registers
All the register operating instructions in the instruction set have direct and single-cycle
access to all registers. The only exception are the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the
LDI instruction for load immediate constant data. These instructions apply to the second
half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND and
OR and all other operations between two registers or on a single register apply to the
entire register file.
As shown in Figure 6, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being phys-
ically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y- and Z-registers can be set to index any
register in the file.
The registers R26..R31 have some added functions to their general-purpose usage.
These registers are address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z are defined as:
Figure 7. X-, Y-, and Z-registers
X - register
Y - register
Z - register
Registers
Purpose
Working
General
15
7
15
7
15
7
7
R29 ($1D)
R27 ($1B)
R31 ($1F)
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
R0
R1
R2
0
0
0
0
7
7
7
Addr.
$0D
$1C
$1D
$00
$01
$02
$0E
$0F
$10
$11
$1A
$1B
$1E
$1F
R28 ($1C)
R26 ($1A)
R30 ($1E)
X-register high byte
Y-register high byte
Z-register high byte
X-register low byte
Y-register low byte
Z-register low byte
0841G–09/01
0
0
0
0
0
0

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