AT90S8535-8AC Atmel, AT90S8535-8AC Datasheet - Page 60
![IC MCU 8K FLSH 8MHZ A/D 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
AT90S8535-8AC
Manufacturer Part Number
AT90S8535-8AC
Description
IC MCU 8K FLSH 8MHZ A/D 44TQFP
Manufacturer
Atmel
Series
AVR® 90Sr
Specifications of AT90S8535-8AC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90S8535-8AC
Manufacturer:
ROHM
Quantity:
6 934
Part Number:
AT90S8535-8AC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
is selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in
UCR is transferred to bit 9 in the Transmit shift register.
On the baud rate clock following the transfer operation to the shift register, the start bit is
shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has been
shifted out, the shift register is loaded if any new data has been written to the UDR dur-
ing the transmission. During loading, UDRE is set. If there is no new data in the UDR
register to send when the stop bit is shifted out, the UDRE flag will remain set until UDR
is written again. When no new data has been written and the stop bit has been present
on TXD for one bit length, the TX Complete flag (TXC) in USR is set.
The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is
cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART
Transmitter will be connected to PD1, which is forced to be an output pin regardless of
the setting of the DDD1 bit in DDRD.
Data Reception
Figure 42 shows a block diagram of the UART Receiver.
Figure 42. UART Receiver
The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times
the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as
the falling edge of a start bit and the start bit detection sequence is initiated. Let sample
AT90S/LS8535
60
1041H–11/01