PIC16C662-04/P Microchip Technology, PIC16C662-04/P Datasheet - Page 61

• Manufacturer Part Number: PIC16C662-04/P
• Description: IC MCU OTP 4KX14 COMP 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C662-04/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 176 B
• Interface Type: RS- 232
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Data Rom Size: 176 B
• Height: 3.81 mm
• Length: 52.26 mm
• Supply Voltage (max): 6 V
• Supply Voltage (min): 4 V
• Width: 13.84 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

9.4.5
PIC16C64X & PIC16C66X devices have on-chip parity
bits that can be used to verify the contents of program
memory. Parity bits may be useful in applications in
order to increase overall reliability of a system.
There are two parity bits for each word of Program
Memory. The parity bits are computed on alternating
bits of the program word. One computation is per-
formed using even parity, the other using odd parity. As
a program executes, the parity is verified. The even
parity bit is XOR’d with the even bits in the program
memory word. The odd parity bit is negated and XOR’d
with the odd bits in the program memory word. When
an error is detected, a reset is generated and the PER
flag bit in the PCON register is set. This indication can
allow software to act on a failure. However, there is no
indication of the program memory location of the failure
of the Program Memory. This flag can only be cleared
in software or by a POR.
The parity array is user selectable during programming.
Bit7 of the configuration word located at address 2007h
can be programmed (read as '0') to disable parity
checking. If left unprogrammed (read as '1'), parity
checking is enabled.
9.4.6
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after POR has expired. Then
the OST is activated. The total time-out will vary based
on oscillator configuration and PWRTE bit status. For
example, in RC mode with the PWRTE bit set (PWRT
disabled), there will be no time-out at all. Figure 9-9,
Figure 9-10
sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-10). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
Table 9-5 shows the reset conditions for some special
registers, while Table 9-6 shows the reset conditions
for all the registers.
TABLE 9-3:
1996 Microchip Technology Inc.
Oscillator Configuration
PARITY ERROR RESET (PER)
TIME-OUT SEQUENCE
XT, HS, LP
RC
and
TIME-OUT IN VARIOUS SITUATIONS
Figure 9-11
72 ms + 1024 T
PWRTE = 0
depict
72 ms
time-out
OSC
Power-up
Preliminary
PIC16C64X & PIC16C66X
PWRTE = 1
1024 T
9.4.7
The power control/status register, PCON (address
8Eh) has four bits. See Figure 4-10 for register.
Bit0 is BOR (Brown-out Reset). BOR is unknown on a
Power-on-reset. It must initially be set by the user and
checked on subsequent resets to see if BOR = '0'
indicating that a Brown-out Reset has occurred. The
BOR status bit is a “don’t care” bit and is not necessar-
ily predictable if the brown-out circuit is disabled (by
clearing the BODEN bit in the Configuration word).
Bit1 is POR (Power-on Reset). It is cleared on a
Power-on Reset and is unaffected otherwise. The user
set this bit following a Power-on Reset. On subsequent
resets if POR is ‘0’, it will indicate that a Power-on
Reset must have occurred.
Bit2 is PER (Parity Error Reset). It is cleared on a Parity
Error Reset and must be set by user software. It will
also be set on a Power-on Reset.
Bit7 is MPEEN (Memory Parity Error Enable). This bit
reflects the status of the MPEEN bit in configuration
word. It is unaffected by any reset or interrupt.
—
OSC
POWER CONTROL/STATUS REGISTER
(PCON)
72 ms + 1024 T
Brown-out Reset
72 ms
OSC
DS30559A-page 61
from SLEEP
1024 T
Wake-up
—
OSC