PIC16C924-08/SP Microchip Technology, PIC16C924-08/SP Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16C924-08/SP
Manufacturer Part Number
PIC16C924-08/SP
Description
IC MCU 64 LD 8MHZ 4K OTP 64-SDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C923-04L.pdf
(189 pages)
4.PIC16LC924-04L.pdf
(10 pages)
Specifications of PIC16C924-08/SP
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-SDIP (0.750", 19.05mm)
For Use With
AC164025 - MODULE SKT PROMATEII 64DIPDVA16XP640 - ADAPTER DEVICE FOR MPLAB-ICE
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C923-04L PDF datasheet #3
- PIC16LC924-04L PDF datasheet #4
- Current page: 15 of 189
- Download datasheet (2Mb)
3.1
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-3.
FIGURE 3-3: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1:
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
4. BSF
5. Instruction @ address SUB_1
1997 Microchip Technology Inc.
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
OSC2/CLKOUT
Clocking Scheme/Instruction Cycle
(RC mode)
SUB_1
PORTA, BIT3 (Forced NOP)
OSC1
Q4
PC
Q2
Q3
Q1
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
Tcy0
PC
Q3
Q4
Execute 1
Fetch 2
Tcy1
Q1
Execute INST (PC)
Fetch INST (PC+1)
Q2
Execute 2
Fetch 3
PC+1
Tcy2
3.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3,
and Q4 cycles. Data memory is read during Q2 (oper-
and read) and written during Q4 (destination write).
Q3
Q4
Execute 3
Fetch 4
Instruction Flow/Pipelining
Tcy3
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Fetch SUB_1 Execute SUB_1
Q2
Flush
Tcy4
PC+2
PIC16C9XX
Q3
Q4
DS30444E - page 15
Tcy5
Internal
phase
clock
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