PIC16F84AT-04/SS Microchip Technology, PIC16F84AT-04/SS Datasheet - Page 657
![IC MCU FLASH 1KX14 EE 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F84AT-04/SS
Manufacturer Part Number
PIC16F84AT-04/SS
Description
IC MCU FLASH 1KX14 EE 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84AT-04/SS
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPI3-DB16F84A - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
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A.3
1997 Microchip Technology Inc.
Transfer Acknowledge
SDA
SCL
Condition
Start
S
All data must be transmitted per byte, with no limit to the number of bytes transmitted per data
transfer. After each byte, the slave-receiver generates an acknowledge bit (ACK)
When a slave-receiver doesn’t acknowledge the slave address or received data, the master must
abort the transfer. The slave must leave SDA high so that the master can generate the STOP con-
dition
Figure A-4:
If the master is receiving the data (master-receiver), it generates an acknowledge signal for each
received byte of data, except for the last byte. To signal the end of data to the slave-transmitter,
the master does not generate an acknowledge (not acknowledge). The slave then releases the
SDA line so the master can generate the STOP condition. The master can also generate the
STOP condition during the acknowledge pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next byte, holding the SCL line low will force
the master into a wait state. Data transfer continues when the slave releases the SCL line. This
allows the slave to move the received data or fetch the data it needs to transfer before allowing
the clock to start. This wait state technique can also be implemented at the bit level,
Figure A-5:
MSB
1
(Figure
Address
2
A-1).
Slave-Receiver Acknowledge
Data Transfer Wait State
acknowledgment
signal from receiver
Transmitter
7
Output by
Output by
SCL from
Receiver
Master
Data
Data
R/W
8
Condition
Start
S
ACK
9
byte complete
interrupt with receiver
Wait
State
1
clock line held low while
interrupts are serviced
1
2
not acknowledge
acknowledge
Data
2
8
Acknowledgment
Clock Pulse for
3 8
acknowledgment
signal from receiver
Appendix A
9
ACK
9
DS31034A-page 34-5
Condition
Stop
P
(Figure
Figure
A-4).
A-5.
34
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