PIC17C43-25E/PQ Microchip Technology, PIC17C43-25E/PQ Datasheet - Page 54
![IC MCU OTP 4KX16 PWM 44-MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC17C43-25E/PQ
Manufacturer Part Number
PIC17C43-25E/PQ
Description
IC MCU OTP 4KX16 PWM 44-MQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C42A-16P.pdf
(241 pages)
3.PIC17C43-16P.pdf
(4 pages)
Specifications of PIC17C43-25E/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
8KB (4K x 16)
Program Memory Type
OTP
Ram Size
454 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-MQFP, 44-PQFP
For Use With
AC164316 - MODULE SKT MPLAB PM3 44MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C43-25E/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C4X
FIGURE 9-2:
TABLE 9-1:
TABLE 9-2:
DS30412C-page 54
Address
RA0/INT
RA1/T0CKI
RA2
RA3
RA4/RX/DT
RA5/TX/CK
RBPU
Legend: ST = Schmitt Trigger input.
10h, Bank 0
05h, Unbanked
13h, Bank 0
15h, Bank 0
Legend: x = unknown, u = unchanged, - = unimplemented reads as '0'. Shaded cells are not used by PORTA.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
Name
Note: I/O pins have protection diodes to V
Name
PORTA
T0STA
RCSTA
TXSTA
Bit0
bit7
bit0
bit1
bit2
bit3
bit4
bit5
RA2 AND RA3 BLOCK
DIAGRAM
PORTA FUNCTIONS
REGISTERS/BITS ASSOCIATED WITH PORTA
Q
Buffer Type
Q
INTEDG
RBPU
SPEN
CSRC
Bit 7
ST
ST
ST
ST
ST
ST
—
CK
D
T0SE
Bit 6
RC9
TX9
—
Input or external interrupt input.
Input or clock input to the TMR0 timer/counter, and/or an external interrupt input.
Input/Output. Output is open drain type.
Input/Output. Output is open drain type.
Input or USART Asynchronous Receive or USART Synchronous Data.
Input or USART Asynchronous Transmit or USART Synchronous Clock.
Control bit for PORTB weak pull-ups.
RD_PORTA
WR_PORTA
SREN
TXEN
T0CS
Bit 5
RA5
Data Bus
SS
(Q2)
(Q4)
.
CREN
SYNC
Bit 4
RA4
PS3
Bit 3
RA3
PS2
—
—
FIGURE 9-3:
FERR
Bit 2
RA2
PS1
Note: I/O pins have protection diodes to V
—
OE = SPEN,SYNC,TXEN, CREN, SREN for RA4
OE = SPEN (SYNC+SYNC,CSRC) for RA5
RA1/T0CKI
Function
OERR
TRMT
Bit 1
PS0
RA4 AND RA5 BLOCK
DIAGRAM
RA0/INT
RC9D
TX9D
Bit 0
—
1996 Microchip Technology Inc.
Serial port output signals
Serial port input signal
0-xx xxxx
0000 000-
0000 -00x
0000 --1x
Power-on
Value on
Reset
DD
RD_PORTA
and V
Data Bus
other resets
Value on all
0-uu uuuu
0000 000-
0000 -00u
0000 --1u
(Note1)
SS
(Q2)
.
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