PIC17LC752T-08/L Microchip Technology, PIC17LC752T-08/L Datasheet - Page 21
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PIC17LC752T-08/L
Manufacturer Part Number
PIC17LC752T-08/L
Description
IC MCU OTP 8KX16 A/D 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Specifications of PIC17LC752T-08/L
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
16KB (8K x 16)
Program Memory Type
OTP
Ram Size
678 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17LC752T-08/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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4.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1 and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-8.
FIGURE 4-8:
EXAMPLE 4-1:
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF
5. Instruction @ address SUB_1
2000 Microchip Technology Inc.
All instructions are single cycle, except for any program branches. These take two cycles since the fetched instruc-
tion is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
OSC2/CLKOUT
Clocking Scheme/Instruction
Cycle
(RC mode)
PORTA, BIT3 (Forced NOP)
OSC1
Q4
PC
Q2
Q3
Q1
CLOCK/INSTRUCTION CYCLE
Q1
INSTRUCTION PIPELINE FLOW
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
T
PC
CY
Q3
0
Q4
Execute 1
Fetch 2
T
CY
1
Q1
Execute INST (PC)
Fetch INST (PC+1)
Q2
Execute 2
Fetch 3
PC+1
T
CY
4.3
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 4-1).
A fetch cycle begins with the program counter incre-
menting in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the Q2,
Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination write).
2
Q3
Q4
Execute 3
Fetch 4
Instruction Flow/Pipelining
T
CY
3
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Fetch SUB_1 Execute SUB_1
Q2
Flush
T
PC+2
PIC17C7XX
CY
4
Q3
Q4
DS30289B-page 21
T
CY
Internal
Phase
Clock
5
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