AT89C51-24JC Atmel, AT89C51-24JC Datasheet - Page 3
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AT89C51-24JC
Manufacturer Part Number
AT89C51-24JC
Description
IC MICRO CTRL 24MHZ 44PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51-24AC.pdf
(17 pages)
Specifications of AT89C51-24JC
Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Number Of I /o
32
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Operating Supply Voltage
0 V to 6.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Peripherals
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51-24JC
Manufacturer:
ATMEL
Quantity:
8 766
Part Number:
AT89C51-24JC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
The AT89C51 provides the following standard features: 4K
bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit
timer/counters, a five vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator and clock cir-
cuitry. In addition, the AT89C51 is designed with static logic
for operation down to zero frequency and supports two
software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning. The
Power-down Mode saves the RAM contents but freezes
the oscillator disabling all other chip functions until the next
hardware reset.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 may also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode P0 has internal
pullups.
Port 0 also receives the code bytes during Flash program-
ming, and outputs the code bytes during program
verification. External pullups are required during program
verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I
Port 1 also receives the low-order address bytes during
Flash programming and verification.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
IL
) because of the internal pullups.
Port 2 pins that are externally being pulled low will source
current (I
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, it uses strong internal pullups
when emitting 1s. During accesses to external data mem-
ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I
Port 3 also serves the functions of various special features
of the AT89C51 as listed below:
Port 3 also receives some control signals for Flash pro-
gramming and verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
pin is also the program pulse input (PROG) during Flash
programming.
In normal operation ALE is emitted at a constant rate of 1/6
the oscillator frequency, and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
IL
IL
) because of the internal pullups.
) because of the pullups.
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
3