AT89LS53-12JI Atmel, AT89LS53-12JI Datasheet - Page 16

• Manufacturer Part Number: AT89LS53-12JI
• Description: IC 8051 MCU FLASH 12K 44PLCC
• Manufacturer: Atmel
• Series: 89LSr

Specifications of AT89LS53-12JI

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: AT89LS5312JI

Figure 9. SPI Transfer Format with CPHA = 1
*Not defined but normally LSB of previously transmitted character
Interrupts
The AT89LS53 has a total of six interrupt vectors: two
external interrupts (INT0 and INT1), three timer interrupts
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
Note that Table 10 shows that bit position IE.6 is unimple-
mented. In the AT89C51 and AT89LV51, bit position IE.5 is
also unimplemented. User software should not write 1s to
Table 10. Interrupt Enable (IE) Register
16
(MSB)
Symbol
User software should never write 1s to unimplemented bits, because
they may be used in future AT89 products.
(FOR REFERENCE)
ET2
ET1
EX1
ET0
EX0
EA
ES
—
(FROM MASTER)
EA
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
SS (TO SLAVE)
(FROM SLAVE)
SCK (CPOL=0)
SCK (CPOL=1)
SCK CYCLE #
—
Position
AT89LS53
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
MOSI
MISO
ET2
Function
Disables all interrupts. If EA = 0, no interrupt
is acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit.
Reserved.
Timer 2 interrupt enable bit.
SPI and UART interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
ES
ET1
*
EX1
MSB
MSB
1
ET0
2
6
6
EX0
(LSB)
3
5
5
these bit positions, since they may be used in future AT89
products.
Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
Figure 10. Interrupt Sources
4
4
4
5
3
3
6
2
2
7
1
1
8
LSB
LSB
0851C–MICRO–3/06