AT91M42800-33AI Atmel, AT91M42800-33AI Datasheet - Page 12

• Manufacturer Part Number: AT91M42800-33AI
• Description: IC ARM7 MCU 144 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M42800-33AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: WDT
• Number Of I /o: 54
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91EB42 - KIT EVAL FOR ARM AT91M42800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: AT91M4280033AI

Embedded ICE
ARM standard embedded In-circuit Emulation is supported
via the JTAG/ICE port. It is connected to a host computer
via an Embedded ICE Interface.
Embedded ICE mode is selected when JTAGSEL is low.
It is not possible to switch directly between ICE and JTAG
operations. A chip reset must be performed (NRST and
NTRST) after JTAGSEL is changed. The reset input to the
Embedded ICE (NTRST) is provided separately to facilitate
debug of boot programs.
IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAG-
SEL is high. The functions SAMPLE, EXTEST and
BYPASS are implemented.
In ICE Debug mode the ARM core responds with a non-
JTAG chip ID that identifies the core to the ICE system.
This is not IEEE 1149.1 JTAG compliant.
It is not possible to switch directly between JTAG and ICE
operations. A chip reset must be performed (NRST and
NTRST) after JTAGSEL is changed.
Memory Controller
The ARM7TDMI processor address space is 4G bytes. The
memory controller decodes the internal 32-bit address bus
and defines three address spaces:
• Internal Memories in the four lowest megabytes
• Middle Space reserved for the external devices (memory
• Internal Peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates
in Little-Endian mode only.
Internal Memories
The AT91M42800 Microcontroller integrates internal
SRAM. All internal memories are 32 bits wide and single-
clock cycle accessible.
The AT91M42800 Microcontroller integrates a primary 8-
Kbyte SRAM bank that is mapped at address 0x0 (after the
remap command), and ARM7TDMI exception vectors
between 0x0 and 0x20 that can be modified by the soft-
ware. The rest of the bank can be used for stack allocation
(to speed up context saving and restoring), or as data and
program storage for critical algorithms.
Boot Mode Select
The ARM reset vector is at address 0x0. After the NRST
line is released, the ARM7TDMI executes the instruction
stored at this address. This means that this address must
be mapped in nonvolatile memory after the reset.
12
or peripherals) controlled by the EBI
AT91M42800
The input level on the BMS pin during the last 10 clock
cycles before the rising edge of the NRST selects the type
of boot memory. The Boot mode depends on BMS (see
Table 4).
The pin BMS is multiplexed with the I/O line PA27 that can
be programmed after reset like any standard PIO line.
Table 4. Boot Mode Select
Remap Command
The ARM vectors (Reset, Abort, Data Abort, Prefetch
Abort, Undefined Instruction, Interrupt, Fast Interrupt) are
mapped from address 0x0 to address 0x20. In order to
allow these vectors to be redefined dynamically by the soft-
ware, the AT91M42800 Microcontroller uses a remap
command that enables switching between the boot mem-
ory and the internal RAM bank addresses. The remap
command is accessible through the EBI User Interface, by
writing one in RCB of EBI_RCR (Remap Control Register).
Performing a remap command is mandatory if access to
the other external devices (connected to chip selects 1 to
7) is required. The remap operation can only be changed
back by an internal reset or an NRST assertion.
Abort Control
The abort signal providing a Data Abort or a Prefetch Abort
exception to the ARM7TDMI is asserted in the following
cases:
• When accessing an undefined address in the EBI
• When the ARM7TDMI performs a misaligned access
No abort is generated when reading the internal memory or
by accessing the internal peripherals, whether the address
is defined or not.
When a write-protected area is accessed, the memory con-
troller detects it, generates an abort and cancels the
access.
When the processor performs a forbidden write access in a
mode-protected peripheral register, the write is cancelled
but no abort is generated.
The processor can perform word or half-word data access
with a misaligned address when a register relative
load/store instruction is executed and the register contains
a misaligned address. In this case, whether the access is in
write or in read, an abort is generated but the access is not
cancelled.
The Abort Status Register traces the source that caused
the last abort. The address and the type of abort are stored
in registers of the External Bus Interface.
BMS
1
0
address space, or writing to a write-protected bank
Boot Memory
External 8-bit memory NCS0
External 16-bit memory on NCS0