ATMEGA128-16AI Atmel, ATMEGA128-16AI Datasheet - Page 218

• Manufacturer Part Number: ATMEGA128-16AI
• Description: IC AVR MCU 128K 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1167170A

Table 89. Status Codes for Master Receiver Mode
Slave Receiver Mode
218
Status Code
(TWSR)
Prescaler Bits
are 0
$08
$10
$38
$40
$48
$50
$58
ATmega128
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
A START condition has been
transmitted
A repeated START condition
has been transmitted
Arbitration lost in SLA+R or NOT
ACK bit
SLA+R has been transmitted;
ACK has been received
SLA+R has been transmitted;
NOT ACK has been received
Data byte has been received;
ACK has been returned
Data byte has been received;
NOT ACK has been returned
In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see
Figure
zero or are masked to zero.
Figure 100. Data Transfer in Slave Receiver Mode
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR
value
SDA
SCL
100). All the status codes mentioned in this section assume that the prescaler bits are
Application Software Response
To/from TWDR
Load SLA+R
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte
TWA6
Device 1
RECEIVER
SLAVE
TWA5
To TWCR
STA
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
TRANSMITTER
Device 2
MASTER
TWA4
0
STO
Device’s Own Slave Address
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
TWINT
Device 3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TWA3
0
TWEA
X
X
X
X
X
0
1
X
X
X
1
X
X
X
TWA2
........
Next Action Taken by TWI Hardware
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to master transmitter mode
Two-wire Serial Bus will be released and not addressed
slave mode will be entered
A START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO flag will
be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO flag will
be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
TWA1
Device n
V
CC
TWA0
R1
TWGCE
R2
2467V–AVR–02/11