ATMEGA323-8AI Atmel, ATMEGA323-8AI Datasheet - Page 184

• Manufacturer Part Number: ATMEGA323-8AI
• Description: IC AVR MCU 32K 8MHZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238AI

Preventing Flash
Corruption
184
ATmega323(L)
• Bit 1 – PGERS: Page Erase
If this bit is set at the same time as SPMEN, the next SPM instruction within four clock
cycles executes page erase. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon comple-
tion of a page erase, or if no SPM instruction is executed within four clock cycles. The
CPU is halted during the entire page erase operation.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If set together with
either ASRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a
special meaning, see description above. If only SPMEN is set, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the
Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon com-
pletion of an SPM instruction, or if no SPM instruction is executed within four clock
cycles. During page erase and page write, the SPMEN bit remains high until the opera-
tion is completed.
Writing any other combination than “10001”, “01001”, “00101”, or “00001” in the lower
five bits will have no effect.
During periods of low V
low for the CPU and the Flash to operate properly. These issues are the same as for
board level systems using the Flash, and the same design solutions should be applied.
A Flash corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly.
Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for
executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one
is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply
2. Keep the AVR core in Power-down sleep mode during periods of low V
voltage. This can be done be enabling the internal Brown-Out Detector (BOD) if
the operating voltage matches the detection level. If not, an external low V
Reset Protection circuit can be used. If a reset occurs while a write operation is
in progress, the write operation will be completed provided that the power supply
voltage is sufficient. The total reset time must be longer than the Flash write
time. This can be achieved by holding the External Reset, or by selecting a long
reset timeout.
will prevent the CPU from attempting to decode and execute instructions, effec-
tively protecting the Flash from unintentional writes.
CC
, the Flash can be corrupted because the supply voltage is too
1457G–AVR–09/03
CC
. This
CC