ATMEGA323-8PI Atmel, ATMEGA323-8PI Datasheet - Page 22

• Manufacturer Part Number: ATMEGA323-8PI
• Description: IC AVR MCU 32K 8MHZ IND 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238PI

The Stack Pointer
Reset and Interrupt
Handling
22
ATmega323(L)
–
SP
The ATmega323 Stack Pointer is implemented as two 8-bit registers in the I/O space
locations $3E ($5E) and $3D ($5D). As the ATmega323 Data memory has $860 loca-
tions, 12 bits are used.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-
rupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by one when
data is pushed onto the Stack with the PUSH instruction, and it is decremented by two
when the return address is pushed onto the Stack with subroutine call and interrupt. The
Stack Pointer is incremented by one when data is popped from the Stack with the POP
instruction, and it is incremented by two when data is popped from the Stack with return
from subroutine RET or return from interrupt RETI.
The ATmega323 provides nineteen different interrupt sources. These interrupts and the
separate Reset Vector, each have a separate Program Vector in the Program memory
space. All interrupts are assigned individual enable bits which must be set (one)
together with the I-bit in the Status Register in order to enable the interrupt. Depending
on the Program Counter value, interrupts may be disabled when Boot Lock bits BLB02
or BLB12 are set. See the section “Boot Loader Support” on page 177 for details
The lowest addresses in the Program memory space are automatically defined as the
Reset and Interrupt Vectors. The complete list of vectors is shown in Table 3. The list
also determines the priority levels of the different interrupts. The lower the address the
higher is the priority level. RESET has the highest priority, and next is INT0
nal Interrupt Request 0, etc. The Interrupt Vectors can be moved to the start of the boot
Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR).
See the GICR description on page 33 for details..
Table 3. Reset and Interrupt Vectors
Bit
$3E ($5E)
$3D ($5D)
Read/Write
Initial Value
Vector No.
1
2
3
4
5
6
7
8
9
SP7
R/W
Program Address
15
R
–
7
0
0
$000
$00A
$00C
$00E
$002
$004
$006
$008
$010
SP6
R/W
14
R
–
6
0
0
(1)
SP5
R/W
(2)
13
R
–
5
0
0
Source
RESET
INT0
INT1
INT2
TIMER2 COMP
TIMER2 OVF
TIMER1 CAPT
TIMER1 COMPA
TIMER1 COMPB
SP4
R/W
12
R
–
4
0
0
SP11
SP3
R/W
R/W
11
3
0
0
Interrupt Definition
External Pin, Power-on Reset,
Brown-out Reset and Watchdog
Reset
External Interrupt Request 0
External Interrupt Request 1
External Interrupt Request 2
Timer/Counter2 Compare Match
Timer/Counter2 Overflow
Timer/Counter1 Capture Event
Timer/Counter1 Compare Match A
Timer/Counter1 Compare Match B
SP10
SP2
R/W
R/W
10
2
0
0
SP9
SP1
R/W
R/W
9
1
0
0
R/W
SP8
SP0
R/W
1457G–AVR–09/03
8
0
0
0
–
the Exter-
SPH
SPL