PIC18C658-E/PT Microchip Technology, PIC18C658-E/PT Datasheet - Page 153
![IC MCU OTP 16KX16 CAN 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C658-E/PT
Manufacturer Part Number
PIC18C658-E/PT
Description
IC MCU OTP 16KX16 CAN 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C658E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 153 of 366
- Download datasheet (7Mb)
15.4.5
In I
located in the lower 7 bits of the SSPADD register
(Figure 15-11). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
FIGURE 15-11: BAUD RATE GENERATOR BLOCK DIAGRAM
FIGURE 15-12: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
2000 Microchip Technology Inc.
2
C Master mode, the reload value for the BRG is
BAUD RATE GENERATOR
SDA
SCL
BRG
value
BRG
reload
SSPM3:SSPM0
03h
SCL
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
02h
SSPM3:SSPM0
SCL is sampled high, reload takes
place and BRG starts its count.
Advanced Information
Control
Reload
01h
CLKOUT
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
Reload
DX-1
remented twice per instruction cycle (T
and Q4 clocks. In I
reloaded automatically. If Clock Arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 15-12).
BRG Down Counter
SSPADD<6:0>
SCL allowed to transition high
03h
2
C Master mode, the BRG is
PIC18CXX8
Fosc/4
02h
DS30475A-page 153
CY
) on the Q2
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