PIC16LC770-E/SO Microchip Technology, PIC16LC770-E/SO Datasheet - Page 180
![IC MCU OTP 2KX14 A/D PWM 20SOIC](/photos/6/64/66480/150-20-soic_sml.jpg)
PIC16LC770-E/SO
Manufacturer Part Number
PIC16LC770-E/SO
Description
IC MCU OTP 2KX14 A/D PWM 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC770-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16LC770E/SO
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PIC16C717/770/771
TABLE 15-22: MASTER SSP I
DS41120B-page 178
Note 1: Maximum pin capacitance = 10 pF for all I
Param.
D102 ‡
100*
101*
102*
103*
106*
107*
109*
No.
110
90*
91*
92*
* These parameters are characterized but not tested. For the value required by the I
‡ These parameters are for design guidance only and are not tested, nor characterized.
2: A Fast mode I
PICmicro
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
[(T
Symbol
T
T
T
T
T
T
SU
T
SU
HD
HD
SU
T
T
HIGH
R
LOW
T
Cb
T
BUF
AA
:
:
:
:
) + (T
R
:
F
STA
DAT
STO
STA
DAT
TM
SU
Mid-Range MCU Family Reference Manual (DS33023).
Characteristic
Clock high time
Clock low time
SDA and SCL
rise time
SDA and SCL
fall time
START condition
setup time
START condition
hold time
Data input
hold time
Data input
setup time
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
:
DAT
2
C bus device can be used in a Standard mode I
) = 1000 + 250 = 1250 ns], for 100 kHz mode, before the SCL line is released.
2
C BUS DATA REQUIREMENTS
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
2
C pins.
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
20 + 0.1Cb
20 + 0.1Cb
TBD‡
4.7 ‡
1.3 ‡
TBD
TBD
Min
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
250
100
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
—
—
—
—
—
—
—
—
0
0
2
C bus system, but (T
1000
3500
1000
Max
300
300
300
300
100
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C specification, please refer to the
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SU
:
DAT
2002 Microchip Technology Inc.
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for Repeated
START
condition
After this period the first clock
pulse is generated
Note 2
Time the bus must be free
before a new transmission
can start
)
250 ns must then be met.
Conditions
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