PIC16LC770-E/SO Microchip Technology, PIC16LC770-E/SO Datasheet - Page 72
![IC MCU OTP 2KX14 A/D PWM 20SOIC](/photos/6/64/66480/150-20-soic_sml.jpg)
PIC16LC770-E/SO
Manufacturer Part Number
PIC16LC770-E/SO
Description
IC MCU OTP 2KX14 A/D PWM 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC770-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16LC770E/SO
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PIC16C717/770/771
9.1
The SPI mode allows eight bits of data to be synchro-
nously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish com-
munication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
9.1.1
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data input sample phase
• Clock edge
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
Figure 9-1 shows the block diagram of the MSSP mod-
ule when in SPI mode.
DS41120B-page 70
(middle or end of data output time)
(output data on rising/falling edge of SCK)
SPI Mode
OPERATION
Advance Information
FIGURE 9-1:
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer Register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR, until the received data is ready. Once the eight
bits of data have been received, that byte is moved to
the SSPBUF register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF
(PIR1<3>), are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the SSP-
BUF register completed successfully.
SDO
SCK
SDI
SS
Read
SS Control
Select
SMP:CKE
Edge
Enable
bit0
Select
Edge
SSPBUF reg
MSSP BLOCK DIAGRAM
(SPI MODE)
Data to TX/RX in SSPSR
Data direction bit
2
SSPSR reg
SSPM<3:0>
2002 Microchip Technology Inc.
Clock Select
4
2
Write
Prescaler
4, 16, 64
Clock
Shift
TMR2 Output
Data Bus
Internal
2
Tosc
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